基于28 nm工艺数字芯片的时钟树设计  

Clock tree synthesis of digital chip based on 28 nm technology

作　　者：陈力颖[1,2] 汤勇 吕英杰[3] CHEN Li-ying;TANG Yong;Lyu Ying-jie(School of Electronics and Information Engineering,Tianjin Polytechnic University,Tianjin 300387,China;Tianjin Key Laboratory of Optoelectronic Detection Technology and Systems,Tianjin Polytechnic University,Tianjin 300387,China;School of Electronic Information and Optical Engineering,Nankai University,Tianjin 300071,China)

机构地区：[1]天津工业大学电子与信息工程学院,天津300387 [2]天津工业大学天津市光电检测技术与系统重点实验室,天津300387 [3]南开大学电子信息与光学工程学院,天津300071

出　　处：《天津工业大学学报》2019年第1期76-82,共7页Journal of Tiangong University

基　　金：天津市应用基础与前沿技术研究计划项目(15JCYBJC16300);天津科技特派员项目(16JCTPJC45500)

摘　　要：针对纳米级设计中时钟偏移大、时序不容易收敛等问题,提出了一种有效的时钟树综合(CTS)优化方案。以28 nm工艺的数字芯片为例,根据其时钟结构特点,将CTS过程分成两步完成。利用这种方法,采用Cadence公司的APR工具Encounter对数字模块进行时钟网络的设计;对分步CTS和传统CTS两种方法进行比较。结果表明:使用分步CTS的时钟偏移减小了52%,提高了时钟网络的性能,从而时序得到了很大的改善,芯片泄漏功耗也降低了45%。An optimized design for clock tree synthesis(CTS)was presented to resolve the large clock skew and timing closure problem of physical design in deep sub-micron technology.Based on a 28 nm digital chip,clock tree synthesis was divided into two steps according to the characteristics of clock structure.What′s more,the APR tool Encounter of Cadence Company was used to design the clock network of digital chip by the optimized method for CTS.The research results showed that the performance of the clock-tree was improved,and the timing was greatly optimized by two-steps CTS.Furthermore,the clock skew was reduced by 52%and the leakage power was reduced by 45%compared with the traditional CTS.

关 键 词：数字芯片 时钟树设计 数字集成电路 物理设计 时钟树综合 时钟偏移 插入延迟 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN47