高速接口JESD204B的灵敏放大器设计  

Sensitive amplifier design for high speed interface JESD204B

作　　者：曹源 张春茗 吕新为 Cao Yuan;Zhang Chunming;LU Xinwei(School of Electronic Engineering,Xi′an University of Posts & Telecommunications,Xi′an 710121,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121

出　　处：《电子技术应用》2019年第5期23-26,共4页Application of Electronic Technique

基　　金：新一代宽带无线移动通信网科技重大专项(2016ZX03001003-006)

摘　　要：采用UMC 28 nm CMOS工艺,在低电源电压下设计实现了一种高速、低失调的灵敏放大器。在传统差分放大器、AB类锁存器等电路的基础上进行改进,提出了一种新型结构的灵敏放大器。利用Cadence软件进行电路设计和功能仿真。仿真结果表明,所设计的电路在1.05 V的低电源电压、5/10 GHz时钟下,其失调电压分别为0.2 mV/0.8 mV,传输延迟分别为50 ps/42 ps,功耗分别为0.37 mW/0.44 mW。因此,所设计的灵敏放大器适用于高速接口JESD204B模数转换模块。This paper introduces a high-speed, low-offset sense amplifier with low supply voltage in UMC 28 nm CMOS process.The paper presents a novel structure of the sense amplifier which bases on the traditional differential amplifier, class AB latch and other circuits. It′ s designed and verified in Cadence. The simulation results show that the proposed design exhibits 0.2 mV/0. 8 mV offset voltage, 63 ps/44 ps delay, 0.37 mW/0.44 mW power dissipation respectively with 1.05 V supply voltage when the clock signal at the 5/10 GHz. Therefore, the proposed sense amplifier is satisfied for the analog-to-digital converter of high-speed interface JESD204B.

关 键 词：灵敏放大器 28 NM CMOS工艺 低电源电压 JESD204B 

分 类 号：TN432[电子电信—微电子学与固体电子学]