时频系统数字锁相技术研究  

Study on Digital Phase Locked Loop in Time Frequency System

作　　者：王鹏宇[1] 杨志刚[1] 郑丽丽[1] WANG Peng-yu;YANG Zhi-gang;ZHENG Li-li(Jhe 27th Research Institute of China Electronics Technology Group Corporation, Zhengzhou 450047, China)

机构地区：[1]中国电子科技集团公司第二十七研究所,郑州450047

出　　处：《电光系统》2019年第1期25-32,共8页Electronic and Electro-optical Systems

摘　　要：文章推导了采用外部1pps信号或10MHz频率信号驯服钮钟或晶振的数字二阶/三阶锁相环结构,建立了频标模块的仿真模型,对模型中的锁相环、数字量化等关键问题进行了分析,给出了参数设置依据及仿真结果,完成了频标模块的硬件设计,验证了模型的正确性。This paper deduces the construction of external 1 pps/10 MHz disciplined rubidium/crystal oscillator by digital 2/3 order phase?locked loop, develops a simulation model of frequency standard module and analyzes several problems about PLL and digital quantitative, and gives a basis for parameter setting and a simulation result and the hardware design is completed and the correctness of the simulation model is verified.

关 键 词：数字锁相环 1pps 频率准确度 频率稳定度 

分 类 号：TN911.8[电子电信—通信与信息系统]