基于硬件加速器的高性能芯片仿真与验证  

Debugging a high-performance WLAN chip with palladium XP emulator

作　　者：王雷[1] 王晨光[1] 吴斌[1] Wang Lei;Wang Chenguang;Wu Bin(Institute of Microelectronics of the Chinese Academy of Sciences,Beijing 100029,China)

机构地区：[1]中国科学院微电子研究所

出　　处：《电子技术应用》2019年第8期61-62,67,共3页Application of Electronic Technique

摘　　要：展示了一款高性能无线局域网芯片采用硬件仿真加速器进行全芯片仿真与验证的工作。该芯片采用了4发4收多天线、256QAM等技术,最高可以实现1.2Gb/s的数据吞吐率。由于该芯片设计复杂,规模庞大,只使用传统的软件模拟和FPGA仿真难以实现芯片错误的快速定位与解决。在此情况下,使用硬件仿真加速器PalladiumXP提供的全电路仿真方式(In-CircuitEmulationmode,ICEmode)成为了更为有效的方式。在实际应用中一个1000帧的测试用例可以在20min内完成,相比传统的软件模拟提高了400倍以上的效率,相比FPGA原型系统验证则能够提供所有所需要的波形供下载分析。该方法大大加快了复杂芯片的设计效率。This paper presents a high-performance wireless local area network(WLAN) chip with throughputs up to 1.2 Gb/s, designed and verified under the help of the Palladium XP emulator. The chip supports 4×4 MIMO and 256-QAM technique, and it is a high-complex and large-scale design. During the debug period, the designers have to wait for a longtime for the software simulator generating the waveform, typically one hour for one frame. However, with the in-circuit emulation(ICE) mode offered by the Palladium XP emulator and the software platform UXE, a 1000-frame testing case can be finished in 20 min and all the important waveform for debugging can be downloaded. The whole verification system greatly improves the design efficiency and helps the digital front-end developing stage finished in time.

关 键 词：硬件仿真 超大规模集成电路设计 数字电路验证 

分 类 号：TN47[电子电信—微电子学与固体电子学]