无人机测控链路位同步环路的设计与FPGA实现  

Design and FPGA Implementation of Bit Synchronization Loop for UAV TT & C Link

作　　者：白园 李成[1] 刘婵[1] 陈飞 BAI Yuan;LI Cheng;LIU Chan;CHEN Fei(No.30 Institute of CETG, Chengdu Sichuan 610041, China)

机构地区：[1]中国电子科技集团公司第三十研究所

出　　处：《通信技术》2019年第10期2555-2561,共7页Communications Technology

摘　　要：在无人机测控系统中,位同步技术处于核心地位,是保证系统正常运行的基础。针对高速率高带宽的无人机测控信号,设计了基于Gardner算法加Farrow结构的位同步环路,首先对所设计的位同步环路的各个模块进行了详细介绍,主要包括内插滤波器模块、定时误差检测模块、环路滤波器模块和控制器模块。然后利用Matlab对系统进行了仿真验证,结果表明系统不仅可以快速计算出最佳采样点的位置,也可以得到具体最佳采样值。最后又将系统编写相应的verilogHDL代码,并首先利用modelsim进行了功能仿真,测试结果与Matlab仿真结果一致,最后将所设计的系统在FPGA平台上进行了测试和实现,结果表明该设计方案稳定、可靠,可直接应用在相关的应用平台上,具有重大的工程实现意义。In the UAV TT&C system, bit synchronization technology is at the core position, which is the basis to ensure the normal operation of the system. For high-rate and high bandwidth UAV measurement and control signals, a bit synchronization loop based on Gardner algorithm and Farrow structure is designed. Firstly, the modules of the designed bit synchronization loop are described in detail, including the interpolation filter module, the timing error detection module, the loop filter module and the controller module. Then the system is simulated and verified by Matlab. The experiment results indicate that this system can not only quickly calculate the position of the best sampling point, but also get the specific optimal sampling value. The corresponding verilog HDL code is written for the system, and the function simulation is performed by modelsim. The test results are consistent with the Matlab simulation results. Finally, the designed system is tested and implemented on the FPGA platform. The results indicate that the design scheme is stable and reliable, and can be directly applied to the relevant application platform, which has significant engineering implementation significance.

关 键 词：GARDNER算法 位同步 内插 误差检测 

分 类 号：TN918[电子电信—通信与信息系统]