基于千兆以太网高速数据记录器传输接口IP核设计  

Design of IP Core for Transmission Interface of High Speed Data Recorder Based on Gigabit Ethernet

作　　者：甄国涌[1] 王琦[1] 焦新泉[1] 储成群[1] ZHEN Guo-yong;WANG Qi;JIAO Xin-quan;CHU Cheng-qun(Key Laboratory of Instrumentation Science & Dynamic Measurement,North University of ChinaTaiyuan,030051,China)

机构地区：[1]中北大学仪器科学与动态测试教育部重点实验室

出　　处：《仪表技术与传感器》2019年第10期39-44,共6页Instrument Technique and Sensor

基　　金：国家自然科学基金项目(61771434)

摘　　要：为了提高数据记录器的传输速度,提出采用千兆以太网进行数据通信。基于FPGA的以太网数据传输是目前应用较为广泛的一种传输手段,但大多数支持千兆以太网的物理芯片并未集成传输协议栈以及接口转换模块,导致其无法直接进行数据传输,针对这一问题,提出利用程序进行IP核设计的解决方案,将以太网MAC层接口以及通信协议报头封装为可根据实际需求对UDP/IP协议栈进行调整的可配置IP核。首先分模块进行流程介绍,之后对其进行封装设计,最后进行结果验证,经验证此IP核速度可达到950Mbit/s,性能较佳。In order to improve the speed of data recorder transmission,gigabit Ethernet was proposed for data communication.Ethernet data transmission based on FPGA was a widely used transmission method at present.However,most of the physical chips supporting gigabit Ethernet did not integrate transmission protocol stack and interface conversion module,which made it impossible to transmit data directly.To solve this problem,a solution of IP core design using program was proposed.The Ethernet MAC layer interface and communication protocol header were encapsulated as configurable IP cores that can adjust UDP/IP stack according to actual requirements.Firstly,this paper introduced the flow of the IP core by modules,then designed the encapsulation of the IP core.Finally,the result verifies that the speed of the IP core can reach 950 Mbit/s,and the performance is better.

关 键 词：以太网 数据传输 UDP/IP协议 IP核 MAC层 媒体独立接口 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]