时频系统数字锁相技术研究  

Study on Digital Phase-Locked Loop in the Time and Frequency System

作　　者：王鹏宇[1] 杨志刚[1] 郑丽丽[1] WANG Peng-yu;YANG Zhi-gang;ZHENG Li-li(The 27 th Research Institute of China Electronics Technology Group Corporation,Zhengzhou 450047,China)

机构地区：[1]中国电子科技集团公司第二十七研究所

出　　处：《宇航计测技术》2019年第5期44-50,共7页Journal of Astronautic Metrology and Measurement

摘　　要：为了利用外部1PPS信号或10MHz频率信号驯服铷钟或晶振,本文推导建立了数字二阶/三阶锁相环频标模块的仿真模型,对模型中的锁相环、鉴相器量化、DA位数、定点运算、环路更新频率对相位噪声性能的影响等关键问题进行了分析,给出了参数设置依据及仿真结果,完成了频标模块的硬件设计,验证了模型的正确性。The construction of the external 1 PPS/10 MHz disciplined Rubidium/Crystal Oscillator by digital 2/3 order phase-locked loop is described in this paper. The Simulation model of frequency standard component is presented,and some key problems about PLL and digital quantitative are analyzed. The parameters set method and simulation result are showed. The hardware design is completed and the testing result verify the correctness of the simulation model.

关 键 词：数字锁相环 秒脉冲(1PPS) 频率准确度 频率稳定度 

分 类 号：TN911.72[电子电信—通信与信息系统]