多栅Fin FET性能研究及参数优化  

Research and Optimization On Multi-Gate FinFET

作　　者：黄宁 刘伟景 李清华 杨婷 HUANG Ning;LIU Weijing;LI Qinghua;YANG Ting(Shanghai University of Electric Power,Shanghai,200090,China;GTA Semiconductor Corporation limited.Shanghai 201306,China;Shanghai Huali Microelectronics Corporation,Shanghai 201203,China)

机构地区：[1]上海电力大学,上海200090 [2]上海积塔半导体有限公司,上海201306 [3]上海华力集成电路制造有限公司,上海201203

出　　处：《电子工业专用设备》2019年第5期61-67,共7页Equipment for Electronic Products Manufacturing

摘　　要：利用TCAD软件搭建高效的双栅及三栅FinFET模型,研究影响多栅器件性能的相关参数。结果显示,随着栅极有效控制面积的增加,器件栅控能力得到明显增强。当三栅FinFET栅长缩减至10nm,鱼鳍高度及鱼鳍宽度分别取Fh=40nm,Fw=5nm时,器件亚阈值参数基本达到理想值:亚阈值斜率(SS)为66.35mV/dec,漏端致势垒降低效应(DIBL)为24mV且由鱼鳍形状引入的拐角效应也得到一定程度上的缓解。最后,以高介电常数(高k)材料HfO2替代传统低介电常数材料SiO2作为三维小尺寸器件的栅氧化层介质,发现HfO2的引入可进一步优化三栅FinFET(Lg=10nm,Fh=40nm,Fw=5nm)亚阈值区域性能:SS下降至61.76mV/dec,DIBL下降至6.47mV。FinFETs with different gate numbers,such as double-gate FinFET(DGFET)and triple-gate FinFET(TGFET),are simulated and analyzed by TCAD.Excellent short channel performance in devices with the value of fin height Fh^40 nm and fin weight Fw^5 nm,i.e.,the almost ideal subthreshold slope(SS)of 66.35 mV/dec and drain induced barrier lowering(DIBL)of 24 mV,is observed while the gate length scaling down to 10 nm and such configuration can also suppressed the corner effect.Furthermore,we found that SS and DIBL can effectively improved by the high-k material HfO2 comparing with the low-k material SiO2,that is,SS and DIBL can be optimized to 61.76 mV/dec and 6.47 mV,respectively.

关 键 词：多栅器件 三栅FinFET 高K栅介质 短沟道效应 

分 类 号：TN432[电子电信—微电子学与固体电子学]