不同介质膜的InP MIS结构界面陷阱的研究  

The Study of Interfacial Traps of InP Metal-Insulator-Semiconductor Structure with Different Insulating Layers

作　　者：卢励吾[1] 周洁[1] 瞿伟[2] 张盛廉[2] 

机构地区：[1]中国科学院半导体研究所半导体超晶格国家重点实验室,北京100083 [2]中国科学院半导体研究所,北京100083

出　　处：《Journal of Semiconductors》1992年第4期225-231,共7页半导体学报（英文版）

摘　　要：对经 PECVD(Plasma Enhanced Chemical Vapor Deposition)生长的不同介质膜 InPMIS结构样品的界而陷阶进行了研究.样品介质膜的生长是在特定实验条件下进行.分别利用C-V(Capacitance-Voltage)和 DLTS(Deep Level Transient Spectroscopy)技术进行研究.结果表明,在介质膜和InP之间InP 一侧有若干界面陷阱存在,获得了与界面陷阱有关的深能级参数.这些陷阱的来源可能是:(1)介质膜淀积过程中InP表面部分P原子挥发造成的P空位;(2)InP衬底材料中的原生缺陷;(3)介质膜淀积过程中等离子体引进的有关辐照损伤.The interfacial traps of InP MIS structure samples with different insulating layers grownby PECVD has been studied using C-V and DLTS technique. The insulating layer was grownunder special conditions. Experimental results show that the interracial traps are located inthe interface between the insulator and InP, and near the interface in the InP.We obtain thedeep level parameters associated with the interfacial traps. The origin of these traps might bedue to (1) During the deposition of insulating layer part of P atoms evaporate and form Pvacancies in InP surface, (2) Native defects in InP substrate, (3) Irradiation damage indu-ced by plasma during insulating layer growth process.

关 键 词：介质膜 MIS结构 界面陷阱 

分 类 号：TN304.055[电子电信—物理电子学]