应用神经网络解决连线总长最短的门阵列布局算法  

Neural Placement Algorithm for Gate Array

作　　者：刘军[1] 兰家隆[1] 王兆明[1] 

机构地区：[1]电子科技大学,成都610054

出　　处：《Journal of Semiconductors》1992年第8期487-492,共6页半导体学报（英文版）

摘　　要：本文研究了利用神经网络来解决VLSI门阵列布局优化问题.文中首先找出了门阵列布局优化问题与神经网络能量函数之间的映射关系,然后利用对应的神经网络动态特性对问题求解.由于神经网络的大规模并行计算特性,使该算法从本质上具有并行处理的特点.In this paper, neural network is used to solve the placement problem for gate array. At first, the mapping relation of the gate array placement optimization problem to the energyfunction of the neural network is found. Then, the dynamic property of this network is usedto solve the placement problem. Because of the large-scale parallel computation of the neu-ral network, this algorithm has the parallel processing property.

关 键 词：神经网络 连线 门阵列 布局模型 

分 类 号：TN711.02[电子电信—电路与系统]