带偏差约束的时钟线网的拓扑构造和优化  

Algorithm for Generating Topology of Skew-Constrained Clock Routing and Optimization

作　　者：刘毅[1] 洪先龙[1] 蔡懿慈[1] 

机构地区：[1]清华大学计算机科学与技术系,北京100084

出　　处：《Journal of Semiconductors》2002年第11期1228-1232,共5页半导体学报（英文版）

基　　金：国家重点基础研究 (编号 :G1 9980 30 4 0 3);国家自然科学基金 (批准号 :6 0 1 6 70 1 6 )资助项目~~

摘　　要：提出了一种新的拓扑构造和优化方法 ,综合考虑了几种拓扑构造方法的优点 ,总体考虑偏差约束 ,局部进行线长优化 .实验结果表明 ,它可以有效控制节点之间的偏差 。A new clock tree topology generation algorithm is proposed for the clock routing.The optimization includes a constructive stage followed by local topology refinement.During the clock tree construction,the skew relationship between clock sinks is considered.Appropriate adjustment to the topology can reduce the delay and skew further.Voronoi diagram is used to accelerate computing.The experimental results show that the algorithm can produce a clock tree with both balanced topology and short wire length.

关 键 词：时钟布线 拓扑构造 时钟偏差 超大规模集成电路 

分 类 号：TN47[电子电信—微电子学与固体电子学]