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作 者:谭德勇 陆聪[1] 杨维明 卫春芳 Tan Deyong;Lu Cong;Yang Weiming;Wei Chunfang(College of Computer Science and Information Engineering,Hubei University,Wuhan 430062,China;College of Knowledge and Practice,Hubei University,Wuhan 430011,China)
机构地区:[1]湖北大学计算机与信息工程学院,武汉430062 [2]湖北大学知行学院,武汉430011
出 处:《计算机测量与控制》2019年第11期275-279,共5页Computer Measurement &Control
摘 要:在分析线性调频(LFM)信号的时频特性和基于直接数字频率合成器(DDS)技术信号产生原理的基础上,选择ALTERA公司的Cyclone II系列的FPGA芯片EP2C70F896C6FPGA,采用ROM查找表技术,利用QuartusII系统提供的PLL锁相环IP核设计系统时钟,设计产生带宽B=10 MHz、时宽T=2.5μs的LFM信号;通过调用Modelsim仿真工具进行RTL仿真验证,FPGA电路仿真的结果与MATLAB仿真结果相符。The time-frequency characteristics of LFM signal were analyzed,and the principle of signal generation based on direct digital frequency synthesizer(DDS)technology was analyzed.On this basis,EP2C70F896C6 FPGA chip of Cyclone II series of ALTERA company was selected,and the PLL phase-locked loop IP core provided by QUARTUSII system was adopted with ROM lookup table technology.The system clock was designed and the LFM signal with bandwidth B=10MHz and time-width was generated.RTL simulation was carried out by calling Modelsim simulation tool.The simulation results of the circuit of the FPGA are consistent with those of the simulation results of the MATLAB.
分 类 号:TP391[自动化与计算机技术—计算机应用技术]
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