适用于3D NAND的高稳定度的Capacitor-free LDO  

High-stable Capacitor-free LDO suitable for 3D NAND

作　　者：万金梅 刘飞 曾子玉 霍宗亮 WAN Jinmei;LIU Fei;ZENG Ziyu;HUO Zongliang(University of Chinese Academy of Sciences,Beijing 100029,China;Institute of Microelectronics,University of Chinese Academy of Sciences,Beijing 100029,China;Yangtze Memory Technologies Co.,Ltd.,Wuhan 430078,China)

机构地区：[1]中国科学院大学,北京100029 [2]中国科学院大学微电子研究所,北京100029 [3]长江存储科技有限责任公司,湖北武汉430078

出　　处：《现代电子技术》2019年第24期42-45,共4页Modern Electronics Technique

基　　金：国家自然科学基金（61474137）;国家重点研发计划(2018YFB1107700)~~

摘　　要：文中设计一种应用于3D NAND的无片外补偿电容的LDO,该电路在传统嵌套米勒补偿的基础上,增加"gm减小电路"和"轻重载控制电路",实现在空载(电流负载为零)且有大负载电容条件下的稳定。此设计应用YMTC 0.18μm工艺实现,仿真结果显示,在2.5~3.6 V电源供电下,整个电路消耗的静态电流为50μA,总补偿电容为7 pF,电路稳定的时间小于6μs,输出线性调整率小于2.2 mV/V,负载调整率小于0.9 mV/mA。A LDO(without external compensation capacitor)applied to 3 D NAND is designed. On the basis of the traditional nested Miller compensation,this circuit adding the "gm reducing circuit" and "light and heavy load control circuit" can realize stabilization under the conditions of no load(current load is zero) and large load capacitor. This design is realized by YMTC 0.18 μm process. The simulation results show that,under the condition of power supply of 2.5~3.6 V,the quiescent current consumed by the whole circuit is 50 μA,the total compensation capacitor is 7 pF,the time of circuit stabilization is less than 6 μs,the output linear adjustment rate is less than 2.2 mV/V,and the load adjustment rate is less than 0.9 mV/mA.

关 键 词：LDO 米勒补偿 3D NAND 电路设计 仿真实验 稳定性分析 

分 类 号：TN911-34[电子电信—通信与信息系统] TP301.6[电子电信—信息与通信工程]