基于FPGA的FSE-CMA盲均衡器设计与实现  

Design and Implementation of FSE-CMA Blind Equalizer Based on FPGA

作　　者：郭业才[1,2] 李峰 万逸儒[1] 胡峥 GUO Yecai;LI Feng;WAN Yiru;HU Zheng(College of Electronic and Information Engineering,Nanjing University of Information Science and Technology,Nanjing 210044,China;Bingjiang College,Nanjing University of Information Science and Technology,Wuxi 214105,Jiangsu,China)

机构地区：[1]南京信息工程大学电子与信息工程学院,南京210044 [2]南京信息工程大学滨江学院,江苏无锡214105

出　　处：《实验室研究与探索》2019年第10期93-99,共7页Research and Exploration In Laboratory

基　　金：国家自然科学基金(61673222,61371131);江苏省高校自然科学研究重大项目(13KJA510001);江苏高校品牌专业建设项目(PPZY2015B134);江苏省教育教学改革项目(2017JSJG168)

摘　　要：针对传统常模盲均衡(CMA)算法相对复杂,太多乘法器导致占用过多逻辑资源的不足,设计并实现了一种基于FPGA的FSE-CMA盲均衡器。给出了盲均衡器的总体框架,设计了硬件电路。以1~20 MHz的DPSK信号为输入信号,设计了数字下变频模块和信号解调模块。改进了FSE-CMA的滤波器结构,设计了硬件实现组成模块及抽头系数更新过程。搭建了硬件测试平台并进行级联了测试与验证。In order to overcome the shortcomings of traditional CMA which has relatively complex structure and too many multipliers,and may lead to too much logic resources,an FSE-CMA blind equalizer based on FPGA is designed and implemented. Firstly,the overall framework of blind equalizer is given and the hardware circuit is designed. Secondly,the digital down-conversion module and signal demodulation module are created,and it takes the DPSK signal of 1 k Hz~ 20 MHz as the input signal. Thirdly,the filter structure of FSE-CMA is improved,and the hardware module and tap coefficient updating process are established. Finally, a hardware test platform is built for cascade testing and verification.

关 键 词：数字下变频 DPSK解调 滤波器结构改进 分数间隔均衡器 

分 类 号：TN911.7[电子电信—通信与信息系统]