一种新型电压倍增电路的设计  

Design of a New Voltage Doubler Circuit

作　　者：侯西亮 罗军[1,2] 李弦 HOU Xiliang;LUO Jun;LI Xian(Institute of Microelec.,Chinese Academy of Sci.,Beijing 100029,P.R.China;Univ.of Chin.Academy of Sci.,Beijing 100049,P.R.China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049

出　　处：《微电子学》2019年第6期802-806,811,共6页Microelectronics

基　　金：国家科技重大专项资助项目(2016ZX02301003002)

摘　　要：为了消除传统电压倍增电路中NMOS管的体效应、电荷回流等问题,提出了一种新型电压倍增电路。采用两相非交叠时钟,通过反相器对PMOS传输管栅极进行动态偏置,消除了NMOS管传输高电压时的阈值损失。采用动态衬底偏置方法,保证内部PN结的反偏,消除了体效应和电荷回流。基于Nor Flash 65 nm工艺进行电路设计,并进行Hspice仿真。结果表明,该电路有效消除了阈值损失和体效应,克服了电荷回流现象,提高了输出电压和工作效率。In order to eliminate the body effect problem and the charge back-flow phenomenon of the traditional NMOS voltage doubler circuit,a new type of voltage doubler circuit was proposed.Two-phase non-overlapping clocks were utilized to dynamically bias the gate of PMOS transistor through inverters,eliminating the threshold loss of NMOS transmission at high voltage.The technology of dynamic substrate bias was used to ensure the reverse bias of the PN junction in PMOS.The charge back-flow and body effect problems were overcome.The circuit was designed in Nor Flash 65 nm technology,and was simulated by Hspice.The simulation results showed that the proposed circuit could effectively eliminate the influence of threshold loss and body effect,and there was no charge back-flow phenomenon,which improved the output voltage and efficiency.

关 键 词：电压倍增电路 体效应 电荷回流 效率 

分 类 号：TN432[电子电信—微电子学与固体电子学]