应用于薄膜透光均匀性检测的锁相电路设计  

A Design of Phase-locked Circuit Applied to Measuring Film Transmissivity Uniformity

作　　者：高忠坚 张锐戈[1] 饶连周[1] 郑华[2] GAO Zhong-jian;ZHANG Rui-ge;RAO Lian-zhou;ZHENG Hua(School of Mechanical and Electronic Engineering,Sanming University,Sanming 365004,China;College of Photonic and Electonic Engineering,Fujian Normal University,Fuzhou350117,China)

机构地区：[1]三明学院机电工程学院,福建三明365004 [2]福建师范大学光电信息学院,福建福州350117

出　　处：《三明学院学报》2019年第6期27-32,共6页Journal of Sanming University

基　　金：福建省中青年教师教育科研项目(JAT160473);三明学院科学研究发展基金项目(B201622);福建省自然科学基金重点项目(JZ160476)

摘　　要：鉴于薄膜透光均匀性检测系统抗干扰能力差、检测信号微弱、输出电压值与输入光信号强度成正比等原因,设计了一款FPGA双通道锁相电路。阐述该设计的组成,在FPGA内部设计的DDS电路和只有3阶的IIR滤波器分别简化了设计,减少了FPGA逻辑资源的使用,最终整个设计能在只有4608个逻辑单元EP2C5T144C8芯片上完成锁相功能。实验结果表明,电路输出与理论分析相吻合,输入输出及幅频特性满足薄膜均匀性检测系统要求。The film transmissivity uniformity detection system appears poor anti-interference ability, the effective detection of weak signals and requirements of detection signals’ amplitude must match closely to optical signal intensity, so that dual-channel phase-locked circuit is designed based on Field-Programmable Gate Array(FPGA). The composition of the design is described in detail in the paper and integrated on the FPGA chip-EP2 C5 T144 C8, which only includes 4608 Logic Elements(LEs). Because both Direct Digital Synthesizer(DDS) circuit and IIR filter with only 3 orders are implemented by FPGA that simplify the whole circuit design and reduce the number of LEs. The experiment results show that the design conforms to the principle of the dual-channel phase-locked circuit. At the same time, the input-output and amplitude-frequency performance of the design are verified well in accordance with requirements of the film transmissivity uniformity detection system.

关 键 词：薄膜均匀度检测 锁相放大器 微弱信号检测 FPGA 

分 类 号：TN402[电子电信—微电子学与固体电子学]