缩短BCH码的快速编译码方法和硬件优化设计  

Fast encoding and decoding method and hardware optimization design for shortened BCH code

作　　者：张多利[1] 姚永彤 宋宇鲲[1] 杜高明[1] ZHANG Duoli;YAO Yongtong;SONG Yukun;DU Gaoming(School of Electronic Science and Applied Physics,Hefei University of Technology,Hefei 230601,China)

机构地区：[1]合肥工业大学电子科学与应用物理学院

出　　处：《合肥工业大学学报（自然科学版）》2019年第12期1655-1660,共6页Journal of Hefei University of Technology：Natural Science

基　　金：国家自然科学基金资助项目(61106020)

摘　　要：文章提出一种缩短Bose-Chaudhuri-Hocquenghem(BCH)码的快速编译码方法,编码过程的计算量为(k-i)(n-k),当i较小时,总计算量为O(nk-k^2),译码过程矩阵复用编码过程矩阵,计算量为0;研究了基准错误图样与码字错误位置对应关系的规律,并从减少错误图样和减少纠错电路的角度,对缩短BCH码的硬件实现进行优化;设计缩短BCH码(36,24,5),该方法在编码过程减少91%的矩阵计算量,减少66.7%的元素个数,译码过程完全省略元素计算过程,错误图样码向量减少11.8%,纠错电路减少51.4%。This paper proposes a fast encoding and decoding method of the shortened Bose-Chaudhuri-Hocquenghem(BCH) code, the total amount of calculation of the encoding process is(k-i)(n-k), when i is small, the total amount of calculation is O(nk-k^2). The decoding process reuses the matrix elements of encoding process, and the amount of calculation is 0. At the same time, the rule of the relation between the error pattern and the error location of the codeword is researched, and the hardware implementation is optimized from the view of reducing the error pattern and reducing the error correction circuit, and a shortened BCH code(36,24,5) is designed. In this paper, the matrix elements in the encoding process is reduced by 91%, the actual effective elements are reduced by 66.7%, and the decoding process can completely ignore the element calculation process. The error pattern is reduced by 11.8% and the error correction circuit is reduced by 51.4%.

关 键 词：缩短BCH码 伴随式 快速编译码 错误图样 汉明重量 

分 类 号：TN919.33[电子电信—通信与信息系统]