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作 者:陈晓亮 陈天 钱忠健 孙伟锋[1] Chen Xiaoliang;Chen Tian;Qian Zhongjian;Sun Weifeng(National ASIC System Engineering Technology Research Center,Southeast University,Nanjing 211189,China;China Resources Microelectronics Limited,Wuxi 214061,China)
机构地区:[1]东南大学国家专用集成电路系统工程技术研究中心,南京211189 [2]无锡华润微电子有限公司,江苏无锡214061
出 处:《半导体技术》2019年第12期938-944,955,共8页Semiconductor Technology
摘 要:在深亚微米CMOS集成电路制造工艺中,应力对MOS器件性能的影响已经不可忽略。应力可以改变半导体载流子的迁移率,因此影响MOS器件的饱和电流。通过对不同版图布局的MOS器件饱和电流进行分析,研究了130 nm CMOS工艺中浅槽隔离(STI)和金属硅化物引起的应力对器件饱和电流的影响。结果表明,器件沟道长度方向的STI应力使PMOS器件饱和电流提高10%左右,同时使NMOS器件饱和电流降低20%~30%;而沟道宽度方向STI应力使NMOS器件饱和电流降低16%~20%,使PMOS器件饱和电流降低14%。相对来说,除了沟道长度方向的金属硅化物拉伸应力对NMOS器件影响较大外,金属硅化物引起的其他应力对MOS器件性能的影响较弱。通过对130 nm CMOS工艺应力的分析,可以指导版图设计,从而改善器件和电路性能。In the deep submicron CMOS integrated circuit manufacturing technology,the effect of stress on performance of MOS devices cannot be ignored.Stresses change the mobility of semiconductor carriers and affect the saturation current of MOS devices.Based on the analysis of the saturation current of MOS devices with different layouts,the influence of the stress induced by shallow trench isolation(STI)and silicide on the saturation current of MOS devices in 130 nm CMOS process was studied.The results show that STI stress in the channel length direction increases the saturation current of PMOS devices by about 10%,meanwhile,it reduces the saturation current of NMOS devices by 20%~30%.STI stress in channel width direction reduces the saturation currents of NMOS devices and PMOS devices by 16%~20%and 14%,respectively.Relatively,except the obvious impact on NMOS device performance from the silicide-induced tensile stress along the channel length direction,other stresses induced by silicide has a weak influence on the performance of MOS devices.Through the analysis of the stress in 130 nm CMOS process,the device layout design can be guided and the device and circuit performance can be improved.
关 键 词:浅槽隔离(STI) 金属硅化物 饱和电流 应力 版图设计
分 类 号:TN386.1[电子电信—物理电子学]
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