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作 者:Sicong Wang Jian Mi Abhishek Vikram Gao Xu Guojie Chen Liming Zhang Pan Liu
机构地区:[1]Yangtze Memory Technologies Co.Ltd,Wuhan,China,430000 [2]Anchor Semiconductor Inc,Santa Clara,USA,95132 [3]Anchor Semiconductor Inc,Shanghai,China,200002
出 处:《Journal of Microelectronic Manufacturing》2019年第4期18-21,共4页微电子制造学报(英文)
摘 要:3D NAND(three-dimensional NAND type)has rapidly become the standard technology for enterprise flash memories,and is also gaining widespread use in other applications.Continued manufacturing process improvements are essential in delivering memory devices with higher I/O performance,higher bit density,and at lower cost.Current 3D NAND technology involves process steps that form array and peripheral CMOS(Complementary Metal-Oxide-Semiconductor)regions side-by-side,resulting in waste of silicon real estate and film stress compromises,and limits the paths of making advanced 3D NAND devices.An innovative architecture was invented to overcome these challenges by connecting two wafers electrically through metal VIAs(Vertical Interconnect Access)[1].Highly accurate and efficient metrology is required to monitor VIA interface due to increased process complexity and precision requirements.With the advanced processing of AFM(Atomic Force Microscopy)images,highly accurate and precise measurements have been achieved.An inline pattern-centric metrology solution that is designed for high volume mass production of high-performance 3D NAND is presented in this paper.
关 键 词:VIA DISHING AFM Image METROLOGY 3D NAND
分 类 号:TP3[自动化与计算机技术—计算机科学与技术]
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