高压As-MOS管用硅外延材料制备工艺的研究  

Study on Silicon Epitaxy Preparation Technology for High-Voltage As-MOS Process

作　　者：李国鹏 马梦杰 金龙 王银海 邓雪华 杨帆 Li Guopeng;Ma Mengjie;Jin Long;Wang Yinhai;Deng Xuehua;Yang Fang(Nanjing Guosheng Electronics CO.,LTD,Jiangsu Nanjing 211111)

机构地区：[1]南京国盛电子有限公司

出　　处：《化工时刊》2019年第12期17-19,共3页Chemical Industry Times

摘　　要：高压As-MOS管用硅外延材料制备工艺的难点在于重掺砷(As)衬底外延的自掺杂和固态外扩散严重,外延电阻率和过渡区不易控制。在多片式外延炉生产时又会因重掺砷衬底之间相互影响,导致相同工艺条件下外延电阻率因片数不同而存在较大差异。本文对不同外延厚度和电阻率产品的片间掺杂效应进行量化分析,确定了不同规格产品的影响幅度,其中高阻薄层产品受影响最大。此外依据自掺杂的产生机理及固体扩散理论,通过二步外延法工艺,有效降低了片间掺杂效应的影响,消除了多片炉生产时因片数不同而产生的参数差异。The difficulty of silicon epitaxy preparation technology for High-Voltage As-MOS Process is referred to heavy autodoping and out-diffusion from heavily dopedarsenic substrates. In addition, because of the out-diffusion among wafers in the same reactor, the resistivity vary from the quantity of the wafers in the same growth condition. In this paper, the calculation and analysis of the effect of wafer-to-wafer autodopingis acted according toepitaxial thickness and resistivity.High resistivity and thin layer displaysheavy effect. Based on autodoping and solid diffusion theory, Wafer-to-wafer autodoping is controlled and the variation of resistivity is eliminated by two-step epitaxial growth and high temperature bake.

关 键 词：硅外延 高阻薄层 片间掺杂效应 电阻率 

分 类 号：TN3[电子电信—物理电子学]