FFT复数处理器设计与FPGA验证  

FFT complex processor design and FPGA verification

作　　者：杨国波 娄皓翔 江礼东 刘跃元 王漕 Yang Guobo;Lou Haoxiang;Jiang Lidong;Liu Yueyuan;Wang Cao(Schoolof Information Scienceand Technology,Chengdu Universityof Technology,Chengdu Sichuan,610059)

机构地区：[1]成都理工大学

出　　处：《电子测试》2020年第2期11-14,共4页Electronic Test

摘　　要：本文介绍了一种基于现场可编程门阵列(FPGA)的快速傅里叶变换(FFT)复数处理器设计,可进行1024点复数计算。采用按时间抽取的基-4算法和基于RAM的蝶形结构。同时对最后一级旋转因子进行了优化,减少了存储器的资源占用。使用流水线的处理结构,控制器简单。最后定点matlab建模与Synopsys的仿真器VCS仿真结果进行了对比,功能正确。完成整个运算仅用了2064个周期。最后用Altera公司的Cyclone IV E系列EP4CE10E22C8芯片完成原型验证,在时钟频率为50MHz时,完成1024点复数FFT仅用41.28μs。A fast Fourier transform(FFT)complex processor design based on field programmable gate array(FPGA)is introduced,which can perform 1024-point complex calculation.A time-decimated base-4 algorithm and a RAM-based butterfly structure are employed.At the same time,the last level of rotation factor is optimized to reduce the memory usage of the memory.Using a pipelined processing structure,the controller is simple.Finally,the fixed-point matlab modeling is compared with the simulation VCS simulation results of Synopsys,and the function is correct.It took only 2064 cycles to complete the entire operation.Finally,prototype verification was performed using Altera’s Cyclone IV E series EP4CE10E22C8 chip.When the clock frequency is 50MHz,the 1024-point complex FFT is only 41.28μs.

关 键 词：FFT处理器 流水线 复数 

分 类 号：TP332[自动化与计算机技术—计算机系统结构] TN791[自动化与计算机技术—计算机科学与技术]