一款高速、低功耗的Sigma-Delta模数转换器  

A High-Speed and Low-Power Sigma-Delta ADC

作　　者：陈昱翀 高博[1] 林志滨 龚敏[1] CHEN Yuchong;GAO Bo;LIN Zhibin;GONG Min(Sichuan Key Lab of Microelectronics Technology,Division of Microelectronics,College of Physical,Sichuan University,Chengdu 610064,China)

机构地区：[1]微电子技术四川省重点实验室四川大学物理学院微电子系

出　　处：《电子与封装》2020年第2期56-60,共5页Electronics & Packaging

摘　　要：提出了一种高速、低功耗、高分辨率的新型Sigma-Delta模数转换器(ADC)结构。该结构选择过采样率(OSR)为32的4阶调制器设计以缓解输出速率和通带宽度的压力,采用级联和双量化的方法进行优化,并利用SIMSIDES工具(基于Simulink的Sigma-Delta仿真器)进行仿真。数字抽取滤波器部分由级联积分梳状(CIC)滤波器、有限长单位冲激响应(FIR)滤波器和半带(HB)滤波器组成,并且三级滤波器都采用了多相分解结构,以降低动态功耗。使用0.18μm的标准CMOS工艺实现数字抽取滤波器版图。仿真结果表明,在250 kHz带宽下,有效位宽(ENOB)为19 bit。A novel structure of Sigma-Delta analog-to-digital converter(ADC)is proposed for high speed,low power consumption and high resolution.The fourth-order modulator with oversampling rate(OSR)of 32 is selected to improve the output rate and passband width.Cascade structure and multi-bit quantizer is applied to the modulator.Then the SIMSIDES tool(Sigma-Delta simulator based on Simulink)can be used for simulating the modulator.The decimation filter consists of cascade integrator comb(CIC)filter,finite impulse response(FIR)filter and half band(HB)filter.The polyphase structure is applied to the decimation filter,which reduces the dynamic power consumption.Finally,a 0.18μm standard CMOS process is used to implement the decimation filter.The simulation results show that the effective number of bits(ENOB)is 19 with the bandwidth of 250 kHz.

关 键 词：SIGMA-DELTA模数转换器 数字抽取滤波器 多相分解 过采样率 

分 类 号：TN492[电子电信—微电子学与固体电子学]