二维网格型粗粒度可重构系统乘法器和全加器设计与验证  

Design and Verification of the Multiplier and the Full Adder of Two-dimensional Grid Coarse Grained Reconfigurable System

作　　者：林谊东 陈乃金 LIN Yidong;CHEN Naijin(School of Electrical Engineering,Anhui Polytechnic University,Wuhu,Anhui 241000;School of Computer and Information Engineering,Anhui Polytechnic University,Wuhu,Anhui 241000)

机构地区：[1]安徽工程大学电气工程学院,安徽芜湖241000 [2]安徽工程大学计算机与信息学院,安徽芜湖241000

出　　处：《绵阳师范学院学报》2020年第2期86-92,共7页Journal of Mianyang Teachers＇ College

基　　金：安徽省自然科学基金面上项目(1808085MF203)

摘　　要：二维网格型粗粒度可重构计算系统具有较高的加速比和较低的功耗,已成为国内外的研究热点,对其计算模块进行设计和验证是二维网格型粗粒度可重构计算系统实用化的关键.本文针对粗粒度可重构计算系统的全加器、乘法器采用Verilog HDL设计语言进行综合设计验证,对二位、四位、八位、十六位、三十二位的乘法器和全加器的动态功耗、结温、硬件资源的使用等进行了分析比较.设计了乘法器原理图和测试代码,实验结果表明:相比较二位全加器,三十二位全加器动态功耗、结温、查找表、I/O分别增大了20.519 w、38.9℃、28个、90个;相比较二位乘法器,三十二位乘法器动态功耗、结温、查找表、I/O个数分别增大了0.603 w、1.1℃、28个、114个.随着位数的增加,全加器动态功耗、结温、查找表、I/O个数的使用消耗较高,但是乘法器动态功耗、结温消耗较低,查找表、I/O个数的使用消耗较高.The two-dimensional grid coarse-grained reconfigurable computing system has become a research hotspot at home and abroad because of its high acceleration ratio and low power consumption.The design and verification of its computing module is the practical key to the practicability of two-dimensional grid coarse-grained reconfigurable computing system.The full adder and multiplier of coarse-grained reconfigurable computing system have been comprehensive designed and verified in this paper.Design language is Verilog HDL.The dynamic power,junction temperature and the use of hardware resources for the multiplier of two bits,four bits,eight bits,sixteen bits,thirty-two bits and the full adder of two bits,four bits,eight bits,sixteen bits,thirty-two bits have been analyzed and compared.The multiplier schematic diagram and the test code are designed.Compard with two bits full adder,the experimental results showed that the dynamic power,junction temperature,look up table and I/O of thirty-two bits full adder increased by 20.519w,38.9℃,28 and 90.Compared with the two bits multiplier,the dynamic power,junction temperature,look up table and I/O of thirty-two bits full adder increased by 0.603w,1.1℃,28 and 114.With the increase of the number of bits,the dynamic power,junction temperature,look up table and the number of I/O of the full-adder had higher consumption.However,the dynamic power,junction temperature of the multiplier had lower consumption,with look up table and the number of I/O higher consumption.

关 键 词：二维网格型粗粒度可重构计算体系结构 全加器 乘法器 动态功耗 结温 查找表、I/O 

分 类 号：TP316[自动化与计算机技术—计算机软件与理论]