基于FPGA的结构改进型(2,1,4)维特比译码器  

FPGA-based structurally improved (2,1,4) Viterbi decoder

作　　者：吴雪玲 江虹[1] Wu Xueling;Jiang Hong(School of Information Engineering,Southwest University of Science and Technology,Mianyang 621000,China)

机构地区：[1]西南科技大学信息工程学院

出　　处：《电子技术应用》2020年第2期43-47,共5页Application of Electronic Technique

基　　金：西南科技大学研究生创新基金

摘　　要：在资源受限的处理器中实现高性能的Viterbi译码算法是近年来研究的热点。基于XC6SLX16-2CSG324型FPGA处理器,在资源有限情况下,为兼顾Viterbi译码时延与资源消耗的问题,提出了一种结构改进算法。在传统Viterbi译码算法基础上,首先通过最大限度地预定义存储路径度量值的寄存器,达到控制路径度量值的目的,其次采用步进式幸存路径信息存储结构,完成幸存路径信息的存储,简化译码器硬件实现复杂度,减小译码时延和资源消耗。通过ISE Design Suite 14.7平台,对回溯深度为20、3 bit软判决的(2,1,4)维比特译码器进行了基于FPGA的验证,并结合MATLAB仿真进行分析。结果表明,本方法能够有效减小译码时延并降低资源消耗。The implementation of high-performance Viterbi decoding algorithm in resource-constrained processors is a hot topic in recent years.This paper is based on the XC6SLX16-2CSG324 type FPGA processor.In the case of limited resources,in order to balance the problem of Viterbi decoding delay and resource consumption,an improved algorithm is proposed.On the basis of the traditional Viterbi decoding algorithm,the purpose of controlling the path metric value is achieved by maximizing the pre-defined storage path metric value register,and then the stepped survivor path information storage structure is used to complete the storage of the surviving path information and simplifying the decoder hardware implements complexity,reducing decoding delay and resource consumption.Based on the ISE Design Suite 14.7 platform,FPGA-based verification of(2,1,4)-dimensional bit decoders with 20-and 3-bit soft-decision depths is performed,and combined with MATLAB simulation.The results show that the method can effectively reduce the decoding delay and reduce the resource consumption.

关 键 词：FPGA VITERBI译码器 度量控制 步进式存储结构 

分 类 号：TN911[电子电信—通信与信息系统]