一种新型动态可重构的正则表达式匹配引擎设计  

A Dynamic Reconfigurable Algorithm for Regular Expression Matching

作　　者：高阳阳 徐烈伟 俞剑 许薇[1] GAO Yangyang;XU Liewei;YU Jian;XU Wei(State Key Laboratory of ASIC&System,Fudan University,Shanghai 201203,China;Shanghai Fudan Microelectronics Group Co.Ltd.,Shanghai 200433,China)

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203 [2]上海复旦微电子集团股份有限公司,上海200433

出　　处：《复旦学报（自然科学版）》2019年第6期706-718,共13页Journal of Fudan University：Natural Science

摘　　要：针对大规模数据处理和动态更新规则的网络计算需求,本文提出了一种新型动态可重构的正则表达式匹配(DRR)算法.算法采用参数化一致性表达方法,提高了正则表达式的动态匹配能力;采用专用电路与可重构电路的混合计算框架,设计了正则表达式匹配的并行计算加速引擎.在软硬件协同工作模式下,新型动态可重构的匹配加速引擎不仅可以最大化利用FPGA电路的可编程特性实现表达式匹配规则的动态更新,提高匹配的预处理速度,设计的专用ASIC并行匹配电路更大幅提高了正则表达式的匹配计算速度.本文采用TSMC 28nm CMOS工艺完成芯片的设计和流片,实验结果表明:本文设计实现的动态可重构的匹配加速引擎可以有效地适用于大多数应用场景下的正则表达式匹配,匹配计算的吞吐率达到280Gb/s,相比于同类型基于FPGA的匹配计算引擎实现了5倍以上的匹配速度提升.To meet the huge demand of large-scale data processing,in this paper,we propose a Dynamic Reconfigurable Regular-expression-matching(DRR)algorithm and a new design of DRR engine.Firstly,a parameterized consistency expression method is designed to improve the dynamic matching capability of various regular expressions.Then,with combined usage of ASIC and FPGA circuits,a novel hybrid-computing framework is designed to construct our new acceleration engine of regular expression matching,where the programmable FPGA circuits are used for quick &dynamic configuration of regular expression and the specifically designed array of elementary processing units are used for parallel processing acceleration.Finally,we implement and fabricate our new acceleration engine(DRR-engine)in TSMC 28 nm CMOS technology.Our experimental results show that,the new DRR-engine has an outstanding performance in regular expression matching with a processing rate of over 280 Gb/s with 1 GHz clock rate,which is 5 times faster than all its counterparts can do.

关 键 词：正则表达式匹配 动态可重构 硬件加速 现场可编程门阵列 

分 类 号：TN402[电子电信—微电子学与固体电子学]