基于FPGA的交换机芯片配置器设计  

The Design of the Switcher’s Chip Configurator Based on FPGA

作　　者：李荣乐 罗长洲[1] 李龙华 李泽超[1] LI Rong-le;LUO Chang-zhou;LI Long-hua;LI Ze-chao(Beijing Research Institute of Control and Electronic Technology,Beijing 100038,China)

机构地区：[1]北京控制与电子技术研究所,北京100038

出　　处：《计算机仿真》2020年第2期41-46,共6页Computer Simulation

摘　　要：高速组合导航信息处理机采用了高速串行RapidIO总线来连接系统中的各功能模块,进行模块间的数据传输。为满足处理机内多点之间互联互通的需求,系统增加了一块SRIO交换板,交换板上CPS1848交换芯片的路由配置成为了研究的关键问题。为解决上述问题,通过分析CPS1848交换芯片的技术特点,提出了一种基于FPGA的交换机芯片配置器技术方案。详细描述了以时序控制模块为核心的由八个模块组成的配置器的组成结构和功能,并采用FPGA集成开发工具ISE对配置器进行了设计与实现。经过仿真验证,结果表明,配置器可通过I^2C总线完成对CPS1848芯片的初始化路由配置,实现系统RapidIO数据包的路由交互传输。A high-speed serial RapidIO bus was used in the integrated high-speed navigation information processor so as to connect various functional modules in the system for data transmission among modules.In addition,in the situation of meeting the needs of multipoint interconnection within the processor,the system was added an SRIO switch board and the routing configuration of CPS1848 switch chip on the switch board became a key problem.To solve the problem,by analyzing the technical characteristics of CPS1848 switch chip,the paper proposes a technical scheme of switch chip configurator based on FPGA.It describes the composition structure and function of a configurator which takes the timing control module as the core and is composed of eight modules in detail.Moreover,the FPGA integrated development tooling ISE was adopted in order to design and implement the configurator.Through simulation verification,the results indicate that the configurator can complete the initial routing configuration of CPS1848 chip via the I2C bus and reach the interactive transmission of RapidIO packet in the system.

关 键 词：高速串行总线 交换芯片 配置器 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]