采用Wallace树优化的分像素运动估计插值滤波算法  

Sub-pixel motion estimation interpolation filtering algorithm based on Wallace tree optimization

作　　者：罗隆 施隆照[1] 洪晓剑 严丹钰 LUO Long;SHI Longzhao;HONG Xiaojian;YAN Danyu(College of Physics and Information Engineering,Fuzhou University,Fuzhou,Fujian 350108,China)

机构地区：[1]福州大学物理与信息工程学院,福建福州350108

出　　处：《福州大学学报（自然科学版）》2020年第2期181-186,共6页Journal of Fuzhou University(Natural Science Edition)

基　　金：福建省自然科学基金资助项目(2018J01801)。

摘　　要：提出一种基于Wallace树优化的HEVC/H.265分像素插值滤波算法的实现方案.模块采用按行流水插值架构,通过Wallace树压缩器对插值过程中的各项进行压缩,仅在最终输出结果时使用加法器.该算法不仅减少了硬件面积,而且提高了模块可工作的最高频率.将所提算法在硬件上进行验证,硬件设计以Verilog HDL语言描述,以8 px×8 px大小PU为最小插值单元,使用Modelsim进行功能仿真验证,在Synopsys Design Compiler中以SAED(Synopsys Armenia education department)32 nm标准单元库进行综合,模块可达到的最高工作频率为636.9 MHz,逻辑门数为32960,吞吐率为11.3 px/时钟周期.This paper presents an implementation scheme of HEVC/H.265 sub-pixel interpolation filtering algorithm optimized by Wallace tree.The implementation adopts a pipelined interpolation architecture and compresses all the items in the interpolation process through the Wallace tree compressor,only the adder is used in the final output.The algorithm not only reduces the hardware area,but also improves the maximum operating frequency.The algorithm proposed has been implemented on hardware which is described by Verilog HDL.The 8 px×8 px PU is chosen as the basic interpolation unit.The function simulation is peformed in Modelsim.The final implementation can operate at frequency of 636.9 MHz and requires 32960 gates when synthesized for SAED(Synopsys Armenia education department)32 nm standard-cell library,gving a throughput of 11.3 px per cycle.

关 键 词：视频编码 HEVC WALLACE树 分像素插值 

分 类 号：TN941.3[电子电信—信号与信息处理]