基于FPGA的分数倍抽取滤波器的改进设计与应用  

Improved Design and Application of Fractional Multiple Decimation Filter Based on FPGA

作　　者：李恩琦 龚小竞[2] 朱卫华[1] 舒承有 陈潮斌 王新林[1] LI Enqi;GONG Xiaojing;ZHU Weihua;SHU Chengyou;CHEN Chaobin;WANG Xinling(School of Electrical Engineering,University of South China,Hengyang,Hunan 421001,China;Research Laboratory for Biomedical Optics and Molecular Imaging,Shenzhen Institute of Advanced Technology,Chinese Academy of Sciences,Shenzhen,Guangdong 518060,China)

机构地区：[1]南华大学电气工程学院,湖南衡阳421001 [2]中国科学院深圳先进技术研究院生物医学光学与分子影像研究室,广东深圳518060

出　　处：《南华大学学报（自然科学版）》2020年第1期52-59,共8页Journal of University of South China：Science and Technology

基　　金：深圳市科技计划项目(JCYJ20160608214524052);中国科学院-威高研究发展计划攻关项目(中科院威高计划[2017]011号);广州大学科研能力提升计划项目(2018A001):深圳市工程实验室项目(介入式诊疗一体化关键技术与工程实验室)。

摘　　要：为了滤除医学超声成像系统中数据采集的噪声,提高图像的完整度,保证图像实时显示帧率及减少FPGA硬件资源的占用,在传统的FIR分数倍抽取滤波器的基础上,提出了一种改进结构。此结构仅利用一个乘法器,解决了传统结构中资源占用多,插值、抽取操作效率低等问题,提高了系统的工作效率和稳定性。通过Matlab、Vivado、Questasim仿真测试及系统成像对比,验证了此结构的可行性,与其他结构滤波器相比,减少了对Dsp、Bram等硬件资源的占用,以满足系统的实际需求。In order to filter out the noise of data acquisition in medical ultrasound imaging system,improve the integrity of the image,ensure the real-time display frame rate of the image and reduce the occupation of FPGA hardware resources,an improved structure is proposed based on the traditional FIR fractional decimation filter.This structure only utilizes a multiplier,which solves the problem of high resource occupation,low interpolation and extraction operation efficiency in the traditional structure,and improves the working efficiency and stability of the system.Through Matlab,Vivado,Questasim simulation test and system imaging comparison,the feasibility of this structure is verified,and compared with other structural filters,the occupation of hardware resources such as Dsp and Bram is reduced to meet the actual needs of the system.

关 键 词：FPGA FIR分数倍抽取滤波器 插值 抽取 资源优化 

分 类 号：TN713[电子电信—电路与系统]