纳米级超大规模集成电路芯片低功耗物理设计分析  

Physical Design and Analysis of Low Power Xonsumption of Nanoscale Vlsi Chips

作　　者：张博文 ZHANG Bo-wen(Yuncheng University,Yuncheng 044000,China)

机构地区：[1]运城学院,山西运城044000

出　　处：《通信电源技术》2020年第6期133-134,共2页Telecom Power Technology

摘　　要：简要介绍了功耗的组成,在此基础上从工艺、电路、门、系统四个层面探讨了纳米级超大规模集成电路的低功耗物理设计方法。提出一种基于Golden UPF的低功耗物理设计过程,为纳米级超大规模集成电路芯片设计人员进行低功耗设计提供参考。It briefly introduces the composition of power consumption,and then discusses the method of low power physical design of nanoscale vlsi from the aspects of process,circuit,gate and system.A low-power physical design process based on Golden UPF is proposed to provide a reference for nanoscale vlsi chip designers in low-power design.

关 键 词：纳米级 超大规模集成电路 电路芯片 电路设计 

分 类 号：TN47[电子电信—微电子学与固体电子学]