Towards functional verifying a family of SystemC TLMs  

作　　者：Tun LI Jun YE Qingping TAN 

机构地区：[1]College of Computer,National University of Defense Technology,Changsha 410073,China [2]Laboratory of Software Engineering for Complex Systems,Changsha 410073,China [3]Jiangnan Institute of Computing Technology,Wuxi 214083,China

出　　处：《Frontiers of Computer Science》2020年第1期53-66,共14页中国计算机科学前沿（英文版）

基　　金：The work was supported by the National Key R&D Program of China(2018YFB1004202);by Laboratory of Software Engineering for Complex Systems.

摘　　要：It is often the case that in the development of a system-on-a-chip(SoC)design,a family of SystemC transaction level models(TLM)is created.TLMs in the same family often share common functionalities but differ in their timing,implementation,configuration and performance in various SoC developing phases.In most cases,all the TLMs in a family must be verified for the follow-up design activities.In our previous work,we proposed to call such family TLM product line(TPL),and proposed feature-oriented(FO)design methodology for efficient TPL development.However,developers can only verify TLM in a family one by one,which causes large portion of duplicated verification overhead.Therefore,in our proposed methodology,functional verification of TPL has become a bottleneck.In this paper,we proposed a novel TPL verification method for FO designs.In our method,for the given property,we can exponentially reduce the number of TLMs to be verified by identifying mutefeature-modules(MFM),which will avoid duplicated veri-fication.The proposed method is presented in informal and formal way,and the correctness of it is proved.The theoretical analysis and experimental results on a real design show the correctness and efficiency of the proposed method.

关 键 词：SYSTEM-ON-A-CHIP TRANSACTION level model SYSTEMC feature-oriented FUNCTIONAL verification 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]