云南高校图书馆联盟文献共享服务平台- SYSTEM-ON-A-CHIP

SYSTEM-ON-A-CHIP: 作品数：10被引量：9H指数：2; 导出分析报告; 相关作者：张轶谦杨长旗蔡懿慈许静宇经彤更多>>; 相关机构：清华大学中国电子科技集团第五十八研究所西安电子科技大学江南大学更多>>; 相关期刊：《Journal of Beijing Institute of Technology》《Frontiers of Computer Science》《Optics and Photonics Journal》《电子器件》更多>>; 相关基金：国家自然科学基金国家重点基础研究发展计划中国科学院科研项目国家高技术研究发展计划更多>>

An attack-immune trusted architecture for supervisory aircraft hardware被引量：2: 《Chinese Journal of Aeronautics》2021年第11期169-181,共13页Dongxu CHENG Chi ZHANG Jianwei LIU Dawei LI Zhenyu GUAN Wei ZHAO Mai XU; supported by the National Key Research and Development Program of China(No.2017YFB0802502);by the Aeronautical Science Foundation(No.2017ZC51038);by the National Natural Science Foundation of China(Nos.62002006,61702028,61672083,61370190,61772538,61532021,61472429,and 61402029);by the Foundation of Science and Technology on Information Assurance Laboratory(No.1421120305162112006);by the National Cryptography Development Fund(No.MMJJ20170106);by the Defense Industrial Technology Development Program(No.JCKY2016204A102);by the Liaoning Collaboration Innovation Center For CSLE,China。; With the wide application of electronic hardware in aircraft such as air-to-ground communication,satellite communication,positioning system and so on,aircraft hardware is facing great secure pressure.Focusing on the s...; 关键词：Aircraft hardware Dynamic integrity measurement Supervisory control System-on-a-Chip(SoC) Trusted computing

Towards functional verifying a family of SystemC TLMs被引量：1: 《Frontiers of Computer Science》2020年第1期53-66,共14页Tun LI Jun YE Qingping TAN; The work was supported by the National Key R&D Program of China(2018YFB1004202);by Laboratory of Software Engineering for Complex Systems.; It is often the case that in the development of a system-on-a-chip(SoC)design,a family of SystemC transaction level models(TLM)is created.TLMs in the same family often share common functionalities but differ in their ...; 关键词：SYSTEM-ON-A-CHIP TRANSACTION level model SYSTEMC feature-oriented FUNCTIONAL verification

System-on-a-Chip (SoC) Based Hardware Acceleration for Video Codec: 《Optics and Photonics Journal》2013年第2期112-117,共6页Xinwei Niu Jeffrey Fan; Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced v...; 关键词：SOC Software PROFILING HARDWARE ACCELERATION Video CODEC

用于SOC测试的一种有效的BIST方法: 《电子器件》2007年第4期1152-1154,共3页须自明刘战王国章于宗光; 电子元器件可靠性物理及其应用技术国防科技重点实验室基金资助(51433020105DZ6802); 为了提高SOC芯片的可测性和可靠性,我们提出了一种SOC测试的BIST技术的实现方案.针对某所自行研制的数字模拟混合信号SOC芯片,我们使用了不同的可测性技术.比如对模拟模块使用改进的BIST方法,对嵌入式存储器使用了MBIST技术.一系列的测...; 关键词：SYSTEM-ON-A-CHIP BIST

A micro amperometric immunosensor for detection of human immunoglobulin: 《Science in China(Series F)》2006年第3期397-408,共12页XU Yuanyuan XIA Shanhong BIAN Chao CHEN Shaofeng; supported by the National Natural Science Foundation of China(Grant No.90307014).; A novel amperometric immunosensor based on the micro electromechanical systems （MEMS） technology, using protein A and self-assembled monolayers （SAMs） for the orientation-controlled immobilization of antibodies, h...; 关键词：amperometric immunosensor micro electromechanical systems （MEMS） self-assembled monolay-ers （SAMs） protein A orientation-controlled immobilization biosensor system-on-a-chip.

Response compaction for system-on-a-chip based on advanced convolutional codes被引量：1: 《Science in China(Series F)》2006年第2期262-272,共11页HAN Yinhe LI Huawei LI Xiaowei ANSHUMAN Chandra; supported in part by the National Basic Research Program of China(973)(Grant Nos.2005CB321604 and 2005CB321605);in part by the National Natural Science Foundation of China(Grant Nos.90207002 and 60576031).; This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a （n, n-1, m, 3） convolutional code is presented. When the proposed theorems ar...; 关键词：SOC test response compaction convolutional code ALIASING X bits masking.

An Efficient Test Data Compression Technique Based on Codes: 《Journal of Semiconductors》2005年第11期2062-2068,共7页方建平郝跃刘红侠李康; 国家高技术研究发展计划(批准号:2003AA1Z1630);国家自然科学基金(批准号:60206006)资助项目~~; This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,t...; 关键词：test data compression unspecified bits assignment system-on-a-chip test hybrid run-length codes

Hardware-Software Co-Simulation for SOC Functional Verification: 《Journal of Beijing Institute of Technology》2005年第2期121-125,共5页严迎建刘明业; SponsoredbytheMinisterialLevelFoundation(K410B066); A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is descri...; 关键词：SYSTEM-ON-A-CHIP CO-SIMULATION instruction set simulator event-driven hardware simulator

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction被引量：3: 《Journal of Computer Science & Technology》2005年第2期201-209,共9页Yin-HeHan Xiao-WeiLi Hua-WeiLi AnshumanChandra; 国家自然科学基金，the Sci. & Technol. Project of Beijing，中国科学院资助项目，Synopsys公司资助项目; This paper presents a test resource partitioning technique based on anefficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor isa single-output compactor, high compaction ratio...; 关键词：system-on-a-Chip (SoC) test resource partitioning (TRP) responsecompaction DIAGNOSE error cancellation

Challenges to Data-Path Physical Design Inside SOC被引量：2: 《Journal of Semiconductors》2002年第8期785-793,共9页经彤洪先龙蔡懿慈许静宇杨长旗张轶谦周强吴为民; 清华大学骨干人才支持计划 ( No.[2 0 0 2 ] 4);国家重点基础研究发展规划 ( No.G-19980 30 40 3)资助项目~~; Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,m...; 关键词：physical design data-path bit-sliced structure SYSTEM-ON-A-CHIP giga-scale integrated circuits very-deep-submicron

SYSTEM-ON-A-CHIP