一种软件化雷达定时器设计方法  

A Software Defined Design Approach for Radar Timer

作　　者：柯小路 杨东华[1] 王继生 李洋[1] KE Xiaolu;YANG Donghua;WANG Jisheng;LI Yang(Nanjing Research Institute of Electronics Technology,Nanjing 210039,China)

机构地区：[1]南京电子技术研究所,南京210039

出　　处：《现代雷达》2020年第3期45-48,共4页Modern Radar

摘　　要：以现场可编程门阵列为平台,提出一种通用定时设计架构,即软件化定时设计方法。它将定时程序划分为软件程序和硬件逻辑两部分,其中硬件逻辑采用定时产生子模块与合成模块实现通用化架构,软件程序为每个子定时配置位置与合成参数,从而实现复杂定时时序的产生。该方法可灵活、快捷调整定时时序,有效提升定时设计与调试效率。Based on field programmable gate array(FPGA),a general framework named software defined timer design approach is proposed.It partitions the timer program into two separate parts,of which the hardware logic is designed to be a general structure consist of sub-timer module and combiner module,and the software program provides count and combination parameters for each sub-timer.The proposed timer design approach is flexible and easy to modify the timing,thus it can significantly improve the efficiency of system design and integration process.

关 键 词：定时器 软件定义 现场可编程门阵列 VERILOG HDL 

分 类 号：TN958[电子电信—信号与信息处理]