一种具有Buffer层的分离栅VDMOS研究  

Research on the Split-Gate VDMOS with Buffer Layer

作　　者：何俊卿 乔明[1] 任敏[1] HE Junqing;QIAO Ming;REN Min(University of Electronic Science and Technology of China,Chengdu 610054,China)

机构地区：[1]电子科技大学,成都610054

出　　处：《电子与封装》2020年第5期56-59,共4页Electronics & Packaging

摘　　要：介绍了一种具有Buffer层的分离栅VDMOS器件,通过Medici进行了仿真研究,分析了Buffer层对器件电学特性的影响,并提供了获得合适Buffer层参数以优化器件功率优值的设计公式。优化后器件的功率优值较现有研究结果均出现了30%以上的增加。A split-gate VDMOS with a buffer layer is introduced.The influence of the buffer layer on the device is analyzed by simulations with Medici,and a design formula for obtaining the appropriate buffer layer parameters to optimize the device power figure of merit is provided.After optimization,the power figure of merit of the device has increased by more than 30%compared with the existing research results.

关 键 词：Buffer层 分离栅VDMOS MEDICI 功率优值 

分 类 号：TN303[电子电信—物理电子学]