一种应用于CMOS图像传感器数字双采样ADC的PGA电路  

A PGA Circuit on Digital Double Sampling ADC of CMOS Image Sensor

作　　者：吴治军[1] 李毅强[1] 彭松 李梦萄 WU Zhijun;LI Yiqiang;PENG Song;LI Mengtao(Chongqing Optoelectronics Research Institute,Chongqing 400060,CHN)

机构地区：[1]重庆光电技术研究所,重庆400060

出　　处：《半导体光电》2020年第2期200-204,共5页Semiconductor Optoelectronics

摘　　要：提出了一种应用于CMOS图像传感器数字双采样模数转换器(ADC)的可编程增益放大器(PGA)电路。通过增加失调采样电容,采集PGA运放和电容失配引入的失调电压,在PGA复位阶段和放大阶段进行相关双采样和放大处理,通过数字双采样ADC将两个阶段存储电压量化,并在数字域做差,降低了PGA电路引入的固定模式噪声。采用0.18μm CMOS图像传感器专用工艺进行仿真,结果表明:在输入失调电压-30~30mV变化区间,提出的PGA的输出失调电压可以降低到1mV以下,相比传统PGA输出失调电压随输入失调电压单倍线性关系而言大大降低了列固定模式噪声。A PGA circuit on digital double sampling ADC of CMOS image sensor is proposed.The offset voltage introduced by mis-matching of amplifier and capacitance of PGA is collected by increasing the offset sampling capacitance CC.The relative double sampling and amplification is performed in the reset sampling and PGA amplification stage,the digital double sampling ADC will quantify the two-stage storage voltage and make the difference in the digital domain,so the fixed mode noise introduced by the circuit of PGA is eliminated.Simulations were performed on 0.18μm special process of CMOS image sensor.The results show that,the output offset voltage of PGA can be reduced to less than 1 mV in the range of input offset voltage of-30~30 mV,which greatly reduces the column FPN compared with traditional PGA with single linear relationship between output offset voltage and input offset voltage.

关 键 词：CMOS图像传感器 数字双采样ADC PGA电路 

分 类 号：TP212[自动化与计算机技术—检测技术与自动化装置]