一种低功耗14 bit逐次逼近型模数转换电路设计  

Design of a Low-power 14 bit Successive Approximation Analog-to-digital Conversion Circuit

作　　者：杨羽佳 黄静[1] 赵继聪 王玉娇 孙玲[1] YANG Yujia;HUANG Jing;ZHAO Jicong;WANG Yujiao;SUN Ling(School of Information Science and Technology,Nantong University,Nantong,Jiangsu,226019,CHN)

机构地区：[1]南通大学信息科学技术学院,江苏南通226019

出　　处：《固体电子学研究与进展》2020年第2期138-144,共7页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(61804084)。

摘　　要：为满足可穿戴集成电路长续航时间的应用需求,设计了一种低功耗14 bit逐次逼近型模数转换电路。为提高电路线性度,采样保持模块利用开关自举原理获得晶体管栅极电压;采用动态预置放大加锁存比较结构,有效降低了比较器模块的功耗;采用分段电容结构,有效减少了数模转换模块的电容数目,节约了芯片版图面积。在Aether软件环境下,采用CSMC 0.18μm CMOS工艺完成了电路的仿真和版图设计,仿真结果表明:电源电压3.3V,输入采样频率为2.08 MHz时,信噪失真比为77.3 dB,有效位数为12.55 bit,电路总功耗为236.4μW,包含I/O焊盘的版图面积为757μm×768μm。A low-power 14 bit successive approximation analog-to-digital conversion circuit was designed to meet the application requirements of wearable integrated circuits for a long-time use.In order to improve the linearity of circuit,the sample-and-hold module used the switch bootstrapping principle to obtain the transistor gate voltage.The power consumption of the comparator module was effectively reduced by using dynamic preamplifier plus latch comparison structure.By using piecewise capacitance structure,the number of capacitors of DAC module was effectively reduced,and the chip layout area was saved.With CSMC 0.18μm CMOS process,the simulation and layout design of the designed circuit were completed in Aether software.The simulation results show that when the power supply voltage is 3.3 V and the input sampling frequency is 2.08 MHz,the signal-to-noise distortion ratio is 77.3 dB,the effective number of bits is 12.55,and the total circuit power consumption is 236.4μW,the layout area is 757μm×768μm including I/O pad.

关 键 词：逐次逼近 模数转换 CMOS工艺 低功耗 IP设计 

分 类 号：TN492[电子电信—微电子学与固体电子学]