一种基于BP最小和译码算法的IP核设计  

An IP core design based on BP minimum-sum decoding algorithm

作　　者：李威 彭端[2] LI Wei;PENG Duan(School of Information Engineering,Guangdong University of Technology,Guangzhou 510006,China;Department of Experimental Teaching,Guangdong University of Technology,Guangzhou 510006,China)

机构地区：[1]广东工业大学信息工程学院,广东广州510006 [2]广东工业大学实验教学部,广东广州510006

出　　处：《现代电子技术》2020年第12期27-29,34,共4页Modern Electronics Technique

基　　金：广东省科技计划项目(2014A010103025)。

摘　　要：基于置信传播BP改进的最小和译码算法原理,依据IEEE 802.11ac标准进行QC-LDPC译码器IP核的设计。对传统BP译码算法的校验节点更新公式进行优化、改进,通过仿真性能对比,采用最小和译码算法设计实现译码器。该译码器采用串行译码结构,可节省硬件资源和开销。在Vivado 2016.4集成开发环境中通过Xilinx ZYNQ7020 FPGA芯片设计码长为648 bit、码率为1/2的QC-LDPC译码器。同时将FPGA实现的译码器输出与计算机仿真结果进行对比,仿真验证结果表明,译码器IP核设计正确合理。On the basis of the principle of the minimum-sum decoding algorithm improved by the confidence propagation BP,the IP core of QC-LDPC decoder is designed according to the IEEE802.11 ac standard. The check node update formula of the traditional BP decoding algorithm is optimized and improved. The decoder is designed and implemented by means of the simulation performance comparison and the minimum-sum decoding algorithm. The serial decoding structure is used for the decoder to save hardware resources and overhead. In the Vivado 2016.4 integrated development environment,a QC-LDPC decoder with code length of 648 bit and code rate of 1/2 is designed by means of the Xilinx ZYNQ7020 FPGA chip. The decoder output achieved by FPGA is compared with the computer simulation results. The simulation verification results show that the IP core design of the decoder is correct and reasonable.

关 键 词：IP核设计 QC-LDPC译码器 最小和译码算法 串行译码结构 性能对比 仿真分析 

分 类 号：TN929.5-34[电子电信—通信与信息系统]