可重构视频阵列处理器测试平台设计与实现  

Design and Implementation of Reconfigurable Video Array Processor Test Platform

作　　者：蒋林 贺飞龙 山蕊 王帅 吴皓月 武鑫 Jiang Lin;He Feilong;Shan Rui;Wang Shuai;Wu Haoyue;Wu Xin(College of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,China;College of Computer Science,Xi’an University of Posts and Telecommunications,Xi’an 710121,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]西安邮电大学计算机学院,陕西西安710121

出　　处：《系统仿真学报》2020年第5期792-800,共9页Journal of System Simulation

基　　金：国家自然科学基金(61772417,61602377,61634004);陕西省科技统筹创新工程(2016KTZDGY02-04-02);陕西省重点研发计划(2017GY-060)。

摘　　要：针对可重构视频阵列处理器的设计要求及传统测试方法测试视频编解码系统时速度慢、精度低和可观测性不强的问题。开发了基于Qt的用户界面,设计实现了以现场可编程门阵列(Field programmable gate-array,FPGA)为核心的软硬件协同测试平台。在PC端实现以软件仿真为基础的数据传输与图像重现,在FPGA端实现以可重构视频阵列处理器为基础的视频编解码算法并行映射。实验结果表明,在工作频率为100 MHz时,FPGA与PC之间可正确传输数据并满足算法测试时不同测试用例的更换需求,具有较好的可观测性。Aiming at the design requirements of the reconfigurable video array processor and the problem of traditional method testing the video codec system with slow speed, low precision and poor observability. A Qt-based user interface is developed, and a hardware-software co-testing platform based on FPGA is designed and implemented. The platform realizes the data transmission and image reproduction based on the software simulation on the PC side, and the parallel mapping of the video encoding and decoding algorithms based on the reconfigurable video array processor on the FPGA side. The experiment results show that the data can be transmitted correctly between FPGA and PC when the working frequency of the platform is 100 MHz, and the replacement demand of the different test cases can be satisfied when the algorithm is tested, and the experiment has a good observability.

关 键 词：测试平台 软硬件协同 用户界面 视频编解码 可重构视频阵列处理器 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]