多电压与扫描链技术在芯片设计中的应用研究  

Research on application of multi-voltage and scan chain technology in chip design

作　　者：向韬鑫 王仁平[1] 刘东明 陈荣林 Xiang Taoxin;Wang Renping;Liu Dongming;Chen Ronglin(College of Physics and Information Engineering,Fuzhou University,Fuzhou 350108)

机构地区：[1]福州大学物理与信息工程学院,福州350108

出　　处：《电气技术》2020年第6期35-38,共4页Electrical Engineering

摘　　要：本文针对芯片中功耗高、测试成本较高的问题进行分析与研究,以一款乘加器为例,该乘加器可以切换在乘、加、乘加3种工作状态。在芯片设计过程中,利用统一标准格式技术实现多电压设计达到低功耗的效果,利用扫描链技术,完成可测试性设计,降低芯片的测试成本,并解决了两种技术的兼容性问题。In this paper,the problem of high power consumption and high cost for test are studied and analyzed.Taking a multiply-add as an example,which can switch between three working states:multiply,add and multiply-add.In the chip design process,the unified power format technology is used to achieve multi-voltage design to achieve low power consumption,and the scan chain technology is used to complete the design for test,reducing the test cost of the chip and solving the compatibility issues of the two technologies.

关 键 词：低功耗 扫描链 多电压 物理设计 统一标准格式 

分 类 号：TN402[电子电信—微电子学与固体电子学]