基于BT5.0的SoC芯片设计技术研究  

Study on Design Technology of BT5.0 SoC Chip

作　　者：董海涛 陈光胜 王晓辉 吴强 DONG Haitao;CHEN Guangsheng;WANG Xiaohui;WU Qiang(Qingdao Eastsoft Communication Technology Co.,Ltd,Shandong 266023,China;Shanghai Eastsoft Microelectronics Co.,Ltd,Shanghai 200235,China)

机构地区：[1]青岛东软载波科技股份有限公司,山东266023 [2]上海东软载波微电子有限公司,上海200235

出　　处：《集成电路应用》2020年第5期5-7,共3页Application of IC

基　　金：青岛市自主创新重大专项项目(18-1-1-99-xcl)。

摘　　要：研究基于BT5.0的SoC芯片的设计技术,提出电源管理模块、复位模块、时钟模块及射频电路模块的设计内容。在芯片设计过程中,采用SoC整合设计,解决了产品小型化、生产可控等问题。采用多层金属工艺平台设计,解决了电感难于集成到芯片内部的技术问题。实现了外围电路简单化,采用多电源域、多工作模式、门控时钟、低功耗单元等设计,解决了芯片应用的低功耗问题;采用SiP技术。实现2.4 GHz和Sub-1 GHz频段的私有协议兼容,拓展了物联网应用场景。The design technology of SoC chip based on BT5.0 is studied,and the design contents of power management module,reset module,clock module and RF circuit module are analyzed.This chip uses SoC integrated design to solve the proBTms of product miniaturization and production controllability;multilayer metal process platform is adopted to solve the technical proBTm that inductance is difficult to integrate into the chip,and the peripheral circuit is simplified;Using multi-power domain,multi-mode,gated clock,low-power unit and so on,the low power proBTm of chip application is solved;and the private protocol compatiBT with 2.4GHz or Sub-1GHz band is realized by using SiP technology and expands the application scenario of the Internet of things.

关 键 词：集成电路设计 蓝牙低功耗 5.0 片上系统 低功耗技术 系统级封装。 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN432