一种用于自适应直方图均衡化的硬件加速器  被引量:4

A hardware accelerator for adaptive histogram equalization

在线阅读下载全文

作  者:陆申阳 冉峰[1] 郭爱英[2] 沈华明 LU Shenyang;RAN Feng;GUO Aiying;SHEN Huaming(Microelectronic Research and Development Center,Shanghai University,Shanghai 200444,China;The New Display Technology and Application of Integrated Key Laboratory of Ministry of Education,Shanghai University,Shanghai 200444,China;School of Mechatronic Engineering and Automation,Shanghai University,Shanghai 200444,China)

机构地区:[1]上海大学微电子研究与开发中心,上海200444 [2]上海大学新型显示技术及应用集成教育部重点实验室,上海200444 [3]上海大学机电工程与自动化学院,上海200444

出  处:《上海大学学报(自然科学版)》2020年第3期401-412,共12页Journal of Shanghai University:Natural Science Edition

基  金:国家自然科学基金研究项目(61376028,61674100);上海市科委重大基础研究项目(16JC1400602)。

摘  要:针对动态直方图均衡(dynamic histogram equalization,DHE)算法处理效果不理想和算法应用不灵活的问题,提出了一种基于改进型自适应直方图均衡化算法的现场可编程逻辑门阵列(field programmable gate array,FPGA)硬件加速器的设计方法.该硬件加速器对直方图均衡化算法做了改进,实现了自适应地限制对比度拉伸;并且充分利用FPGA的并行体系架构和丰富的块存储资源的优点,采用规则的模块化的设计方法完成了设计.实验结果表明:改进的算法不会产生过度增强、放大噪声、丢失图像细节的现象;设计的硬件加速器在充分节约硬件资源的前提下能较好地满足实际应用的需求;在实时图像处理中一帧图像的处理时间约为0.1 ms,使图像增强算法在图像实时处理中的应用更加灵活方便.In order to solve the problem that the dynamic histogram equalization(DHE)algorithm does not work well and that the algorithm cannot be applied flexibly,a field programmable gate array(FPGA)-based hardware accelerator design method for improved adaptive histogram equalization algorithm is proposed.The hardware accelerator improves the histogram equalization algorithm and adaptively limits the contrast stretch.It is designed in modularity after taking full advantage of the parallel architecture and abundant block storage resources that FPGA has.Experiment results show that the improved algorithm does not result in excessive enhancement,noise amplification and loss of image detail.The proposed hardware accelerator not only performs well in saving hardware resources but is effective as well in practical application.In real-time image processing,it takes only about 0.1 milliseconds for the processing of a frame image,thus making the image enhancement algorithm in real-time image processing more easily accessible.

关 键 词:现场可编程逻辑门阵列 自适应 直方图 硬件加速器 

分 类 号:TP391[自动化与计算机技术—计算机应用技术]

 

参考文献:

正在载入数据...

 

二级参考文献:

正在载入数据...

 

耦合文献:

正在载入数据...

 

引证文献:

正在载入数据...

 

二级引证文献:

正在载入数据...

 

同被引文献:

正在载入数据...

 

相关期刊文献:

正在载入数据...

相关的主题
相关的作者对象
相关的机构对象