改进Cholesky分解算法的设计与FPGA实现  

Design and FPGA Implementation of an Improved Cholesky Factorization Algorithm

作　　者：李丽 张巍 LI Li;ZHANG Wei(Unit 91001 of PLA,Beijing 100071,China;Southwest China Institute of Electronic Technology,Chengdu 610036,China)

机构地区：[1]解放军91001部队,北京100071 [2]中国西南电子技术研究所,成都610036

出　　处：《电讯技术》2020年第7期845-849,共5页Telecommunication Engineering

摘　　要：针对大规模数字阵列的空域信号处理以及空时信号处理的要求,提出了一种高速并行的基于Cholesky分解的协方差矩阵反问题求解算法。相对于其他现有算法,所提算法具有更高的并行度与更低的处理延迟。在算法实现方面,提出了一种基于脉动阵列+反馈环的矩阵迭代结构来实现该算法,并在现场可编程门阵列(Field Programmable Gate Array,FPGA)平台上验证了该结构的有效性。电子设计自动化(Electronic Design Automatic,EDA)工具的综合与实现结果表明,所提算法实现结构具有高并行性、低延迟等优势,尤其在矩阵规模相对较大时优势明显。According to the requirements of large-scale spatial and space-time array signal processing,a high-speed parallel algorithm based on Cholesky factorization is proposed to solve the inverse problem of covariance matrix.Compared with other existing algorithms,the proposed algorithm has higher parallelism and lower processing delay.In the aspect of implementation,a matrix iterative structure based on systolic feedback loop is proposed and verified on field programmable gate array(FPGA)platform.Finally,the synthesis and implementation results of EDA tools show that the proposed algorithm architecture has the advantages of high parallelism and low delay,especially when the matrix is relatively large.

关 键 词：阵列信号处理 CHOLESKY分解 脉动阵列 矩阵迭代结构 

分 类 号：TN911.7[电子电信—通信与信息系统]