基于Zynq SoC的EtherCAT主站设计及实现  

Design and Implementation of EtherCAT Master Based on the Zynq SoC

作　　者：马平[1] 苏攀杰 刘胜旺 邓龙军 MA Ping;SU Pan-jie;LIU Sheng-wang;DENG Long-jun(School of Electromechanical Engineering,Guangdong University of Technology,Guangzhou 510006,China;GSK CNC Equipment Co.,Ltd.,Guangzhou 510535,China)

机构地区：[1]广东工业大学机电工程学院,广州510006 [2]广州数控设备有限公司,广州510535

出　　处：《组合机床与自动化加工技术》2020年第7期122-126,共5页Modular Machine Tool & Automatic Manufacturing Technique

基　　金：广东省重点领域研发计划项目(2019B090918002);高档数控机床与基础制造装备(2018ZX04006001-010)。

摘　　要：为了在高端数控系统中实施高性能的EtherCAT总线,提出了一种基于Zynq-7000 SoC的EtherCAT主站构建方案。首先基于Zynq-7000硬件平台,运用系统模块化设计方法对EtherCAT主站进行总体方案规划,然后基于电子设计平台Vivado设计主站的硬件工程,接着在CPU0上搭建FreeRTOS操作系统,在此基础上移植了开源主站库(SOEM-1.3.3)并对网卡驱动进行优化,最后建立了EtherCAT主站测试系统。实验结果表明,该主站的周期通信时间约为40μs,通信抖动为纳秒级,具有较高的实时性和稳定性。In order to implement high performance EtherCAT bus in high-end CNC system, a construction scheme of EtherCAT master based on Zynq-7000 SoC is proposed. Firstly, based on Zynq-7000 hardware platform, the system modularization design method is used to plan the EtherCAT master. Then, the master′ hardware project is designed by Vivado electronic design platform, and the FreeRTOS is built in CPU0. On this basis, the open source master library(SOEM-1.3.3) is transplanted and the network driver is optimized. Finally, the EtherCAT master test system is established. The results show that the cycle time of the master is about 40μs, and the jitter of the master is nanosecond, which has high real-time performance and stability.

关 键 词：EtherCAT主站 Zynq芯片 FREERTOS 

分 类 号：TH16[机械工程—机械制造及自动化] TG659[金属学及工艺—金属切削加工及机床]