一种动态可配置二维CFAR处理器的设计与实现  

Design and Implementation of a Runtime-Configurable Two-Dimensional CFAR Processor

作　　者：高巍 杨昊 蒋荣堃 谢芳 周哲 王晓华[1] GAO Wei;YANG Hao;JIANG Rong-kun;XIE Fang;ZHOU Zhe;WANG Xiao-hua(School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China)

机构地区：[1]北京理工大学信息与电子学院,北京100081

出　　处：《北京理工大学学报》2020年第7期797-802,共6页Transactions of Beijing Institute of Technology

摘　　要：为实现多场景下二维恒虚警(CFAR)算法的硬件加速,提出了一种基于FPGA平台的动态可配置二维CFAR处理器实现结构.该处理器实现了单元平均(CA)、最大选择(GO)、最小选择(SO)及有序统计(OS)4种二维矩形窗检测器的流水运算.通过参数的控制,该处理器支持参考窗尺寸、保护窗尺寸及检测器类型等可配置.对于256×512点二维检测数据,该处理器各检测器的运算时间均小于3 ms,检测门限相对误差不超过0.1%.验证结果表明该处理器能较好地完成雷达二维检测数据的恒虚警检测工作.A hardware architecture of runtime-configurable two-dimensional constant false alarm rate CFAR processor was proposed based on FPGA to improve the algorithm speed for multi-scenario.This processor was designed to implement four pipeline architecture operations,cell averaging(CA),greatest of(GO),smallest of(SO)and ordered statistics(OS),for two-dimensional rectangular window(2D-RW)detectors.Also,controlling correlative parameters,this processor could make the reference window size,guard window size and detector type configurable.Test results show that,for 256×512 points data,the computation time of each detector in the processor is less than 3ms,and the relative error of detection threshold is no more than 0.1%,validating its better detection ability for two-dimensional radar data.

关 键 词：雷达目标检测 二维恒虚警 现场可编程逻辑门阵列 动态可配置 

分 类 号：TP957[自动化与计算机技术]