Tile型三角形多向并行扫描算法的设计  

Design of multi-directional and parallel triangle scanning algorithm of Tile

作　　者：樊萌 蒋林 杨博文 郭佳乐 田璞 FAN Meng;JIANG Lin;YANG Bo-wen;GUO Jia-le;TIAN Pu(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,China;Integrated Circuit Design Laboratory,Xi’an University of Science and Technology,Xi’an 710054,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]西安科技大学,集成电路设计实验室,陕西西安710054

出　　处：《计算机工程与设计》2020年第8期2360-2366,共7页Computer Engineering and Design

基　　金：国家自然科学基金项目(61834005、61772417、61802304、61272120、61602377、61634004);陕西省科技统筹创新工程基金项目(2016KTZDGY02-04-02);陕西省国际科技合作计划基金项目(2018KW-006);陕西省重点研发计划基金项目(2017GY-060)。

摘　　要：针对图形处理器中光栅化对三角形处理速度的高要求,提出一种基于Tile的三角形多向并行扫描算法。以2×2大小的像素块作为扫描像素块的尺寸,采用并行方式一次处理16个像素,完成在Tile内对三角形内部像素的遍历。对不同种类的三角形进行实验分析与性能对比,其结果表明,该算法能够显著提高三角形的遍历速度,使得扫描填充率最大可达100%。采用Xilinx公司的ISE开发环境对硬件电路进行FPGA测试,实验结果表明,该方法可以正确且高效实现三角形遍历功能,适用于高性能的图形处理器。For the high speed requirements of processing triangles during rasterization in graphics processor,an algorithm of multi-directional and parallel triangle scanning based on Tile was proposed.A 2 pixel×2 pixel unit block was used as the size of the scan unit block,and 16 pixels were parallel processed at one time to complete the traversal of the triangle internal pixels in a Tile.By experimentally analyzing and performance comparing of different kinds of triangles,it can be found that the proposed algorithm can significantly improve the traversal speed of the triangles,and the maximum filling rate reaches 100%.The Xilinx ISE development environment was used to test the hardware design in FPGA(field-programmable gate array).The test results show that the design can implement the triangle traversal correctly and efficiently,and it is suitable for high performance grap-hics processors.

关 键 词：图形处理器 光栅化 分块 三角形遍历 现场可编程门阵列 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]