嵌入式SRAM MBIST优化设计研究  

Research on the optimized design of embedded SRAM MBIST

作　　者：姜爽 刘诗斌[1] 郭晨光 喻贤坤 JIANG Shuang;LIU Shi-bin;GUO Chen-guang;YU Xian-kun(School of Electronics and Information,Northwestern Polytechnical University,Xi'an 710072,China;Beijing Microelectronics Technology Institute,Beijing 100076,China)

机构地区：[1]西北工业大学电子信息学院,陕西西安710072 [2]北京微电子技术研究所,北京100076

出　　处：《微电子学与计算机》2020年第8期37-42,共6页Microelectronics & Computer

摘　　要：随着制造工艺的进步和SoC功能的日益丰富,现代SoC大多会集成大量不同种类的嵌入式SRAM,三单元耦合故障对电路的影响开始加深.传统MBIST通常基于EDA工具直接实现,以检测单、双单元故障为主,无法全面覆盖三单元耦合故障,应用于现代SoC时还面临测试开销过大,测试覆盖率低等问题.通过提出一种针对三单元耦合故障,以及基于嵌入式SRAM的大小、类型、数量和版图布局的精细化MBIST优化设计方法,实现了SoC芯片面积和测试时间的平衡和优化,降低了测试成本并提升了测试覆盖率.With the progress of manufacturing technology and the increasing of system-on-chip circuit functions, most modern system-on-chip integrate a variety of embedded static random-access memory, and the influence of three-cell coupling faults begins to deepen. The traditional memory built-in self-test method is usually implemented directly on the basis of electronic design automation tools, which is mainly used for detecting single and double cell faults, and the three-cell coupling faults cannot be comprehensively covered, and the problems of excessive testing overhead and low test coverage are also faced in the application of the modern system-on-chip. In this paper, a memory built-in self-test optimization design method for three-cell coupling faults based on the size, type, quantity and layout of embedded SRAM is proposed, which realize the balance and optimization of the scale and test time of SoC chip, reduce the test cost and increase the test coverage.

关 键 词：SRAM MBIST 三单元耦合故障 测试成本 测试覆盖率 

分 类 号：TN4[电子电信—微电子学与固体电子学]