基于Verilog HDL语言的一种奇偶校验码与极化码级联的编码器设计与仿真  

Design and Simulation of a Concatenation of Parity Check Code and Polarization Code Based on Verilog HDL Language

作　　者：彭逸飞 PENG Yi-fei(UESTC,School of Communication and Information Engineering,Chengdu 611731,China)

机构地区：[1]电子科技大学信息与通信工程学院,四川成都611731

出　　处：《通信电源技术》2020年第11期107-110,114,共5页Telecom Power Technology

摘　　要：极化码(Polar Code)将信道极化为一类信道容量几乎接近于1和一类信道容量几乎趋近于0的两类信道。通过极化得到的信道容量趋近于1的信道,是目前理论上唯一能够被严格证明可以达到香农极限的编码方案。为了降低极化码对循环冗余检验(Cyclic Redundancy Check,CRC)的额外硬件开销,本文根据奇偶校验码(Parity-Check-Concatenated,PCC)与极化码级联的编码方案,提出了一种基于Verilog的PCC的FPGA编码方案。仿真结果证明,该方案在两种校验模式下均可使用。Polar code polarization codepolarizes the channel into two types of channels with a channel capacity close to 1 and another channel capacity close to 0. The channel whose channel capacity is close to 1 by polarization is the only coding scheme that can be strictly proved to reach Shannon’s limit. In order to reduce the additional hardware overhead of Polar code for CRC Cyclic Redundancy Check cyclic redundancy circuit this paper proposes a coding scheme based on the concatenation of parity-check-concatenated PCC and polarization codes. FPGA coding scheme based on Verilog’s PCC polar code. Simulation results prove that the scheme can be used in both verification modes.

关 键 词：PCC CRC 极化码 VERILOG VIVADO 

分 类 号：TN911.22[电子电信—通信与信息系统]