一种基于BSIM4的屏蔽栅沟槽MOSFET紧凑型模型  

A compact model of shield-gate trench MOSFET based on BSIM4

作　　者：江逸洵 乔明[1] 高文明 何小东 冯骏波 张森 张波[1] Jiang Yi-Xun;Qiao Ming;Gao Wen-Ming;He Xiao-Dong;Feng Jun-Bo;Zhang Sen;Zhang Bo(State Key Laboratory of Electronic Thin Film and Integrated Devices,University of Electronic Science and Technology of China,Chendu 610054,China;CSMC Technologies Corporation,Wuxi 214028,China)

机构地区：[1]电子科技大学,电子薄膜与集成器件国家重点实验室,成都610054 [2]无锡华润上华科技有限公司,无锡214028

出　　处：《物理学报》2020年第17期201-212,共12页Acta Physica Sinica

摘　　要：提出了一种基于BSIM4的屏蔽栅沟槽MOSFET紧凑型模型.在直流模型中使用两端电势建立JFET区等效电阻模型,并引入电子扩散区等效电阻,解决了因忽视JFET区源端电势导致的电流存在误差的问题.在电容模型中,漏源电容模型在BSIM4的基础上添加了屏蔽栅-漏等效电容模型,栅漏电容模型将栅漏偏置电压修改为栅极同栅-漂移区重叠区末端节点的电势差.使用泊松方程求解该节点电势,并引入栅氧厚度因子k1、屏蔽栅氧化层厚度因子k2、等效栅-漂移区重叠长度Lovequ和等效屏蔽栅长LSHequ对栅和屏蔽栅的结构进行等效,以简化泊松方程的计算并确保该节点电势曲线的光滑性.使用Verilog-A编写模型程序,搭建实验平台测试屏蔽栅沟槽MOSFET的直流特性、电容特性和开关特性,模型仿真结果与测试数据有较好的拟合,验证了所建模型的有效性.Shield-gate trench MOSFET in a low-to-medium voltage range(12-250 V)plays a key role in the power conversion market due to its low power loss caused by the sheild-gate structure.In order to eliminate the faults resulting from the parasitic effects of the device and improve the conversion efficiency,the device model is indispensable in designing a circuit system.In this paper,a compact model of shield-gate trench MOSFET based on BSIM4 is proposed,including the DC model and the capacitance model.In the DC model,the basic MOSFET structure uses BSIM4,and the equivalent resistances of the basic MOSFET in series are divided into three parts.The equivalent resistance model of JFET region is established by using the electric potential difference between both ends for the first time,and the equivalent resistance model of electron diffusion region is also introduced,in order to solve the problem of current error caused by neglecting the source potential of JFET region.The equivalent resistance between drain and JFET region and the equivalent resistance of electron diffusion region both prove to be constant.In the capacitance model based on BSIM4,the model of shield-gate to drain capacitance is added to the model of drain to source capacitance,and the voltage bias between drain and gate in the model of gate to drain capacitance is modified into the potential difference between the node at the end of the gate-drift overlap region and the gate.Poisson equations are used to solve the electric potential of this node.Furthermore,the gate oxide thickness factor k1,the shield-gate oxide thickness factor k2,the equivalent length of gate-drift overlap Lovequ and the equivalent length of shield-gate LSHequ are introduced to redefine the position of gate and shield-gate,thereby simplifying the Poisson equations and ensuring the smoothness of the potential curve of the node.Comparison of the data from the simulation by using Verilog-A program with the test results from the experimental platform shows that the model simulation results f

关 键 词：屏蔽栅沟槽MOSFET 紧凑型模型 BSIM4 VERILOG-A 

分 类 号：TN386[电子电信—物理电子学]