Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors  

作　　者：Xiaoqiao DONG Ming LI Wanrong ZHANG Yuancheng YANG Gong CHEN Shuang SUN Jianing WANG Xiaoyan XU Xia AN 

机构地区：[1]Key Laboratory of Microelectronic Devices and Circuits,Institute of Microelectronics,Peking University,Beijing 100871,China [2]Faculty of Information Technology,Beijing University of Technology,Beijing 100124,China

出　　处：《Science China(Information Sciences)》2020年第10期284-286,共3页中国科学（信息科学）（英文版）

基　　金：supported in part by National Key Research and Development Plan(Grant No.2016YFA0200504);National Science and Technology Major Project(Grant No.2017ZX02315001-004);Program of National Natural Science Foundation of China(Grant Nos.61421005,61774012,61574010);Beijing Innovation Center for Future Chips Foundation(Grant No.KYJJ2016008);the 111 Project(Grant No.B18001)。

摘　　要：Dear editor,With the development of VLSI technology,gateall-around(GAA)silicon nano wire transistor(SNWT)has emerged as one of the most potential candidates for ultimately scaled CMOS devices at the end of the technology roadmap.Some pioneering research studies have demonstrated super scalability and high performance with GAA SNWT[1-3].

关 键 词：GAA TRANSISTOR asymmetrical 

分 类 号：TN32[电子电信—物理电子学]