面向嵌入式的可重构FFT的硬件实现  

Hardware implementation of reconfigurable FFT for embedded system

作　　者：张翌 刘有耀 焦继业 ZHANG Yi;LIU Youyao;JIAO Jiye(School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121,China;School of Computing,Xi’an University of Posts and Telecommunications,Xi’an 710121,China)

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121 [2]西安邮电大学计算机学院,陕西西安710121

出　　处：《电子设计工程》2020年第21期178-183,共6页Electronic Design Engineering

基　　金：国家自然科学基金资助项目(61874087)。

摘　　要：针对实时嵌入式应用,提出了一种采用Radix-2算法的可重构FFT硬件加速器结构。该结构一次可并行处理16点FFT,且可在不改变电路结构的情况下,通过修改相应的配置信息来实现16-1024点FFT。该结构的硬件利用率为100%,整个设计采用Synopsys VCS仿真,在100 MHz工作频率下,对于1024点16位复数定点FFT仅需要38.6μs,与Cortex M4的DSP相比速度提升了94%以上。经DC综合结果表明在SMIC 0.11μm工艺中,该结构的核心面积为0.98 mm2,可用于嵌入式设备中。For real⁃time embedded applications,a reconfigurable FFT hardware accelerator structure using Radix⁃2 algorithm is proposed.The structure can process 16 point FFT in parallel at one time,and can realize 16-1024 point FFT by modifying the corresponding configuration information without changing the circuit structure.The hardware utilization rate of the structure is 100%.The whole design adopts Synopsys VCS simulation.At 100 MHz working frequency,it only needs 38.6μs for 1024 point 16 bit complex fixed⁃point FFT,and the speed is increased by 94%compared with the DSP of Cortex M4.The DC synthesis results show that in SMIC 0.11μm process,the core area of the structure is 0.98 mm2,which can be used in embedded equipment.

关 键 词：嵌入式 可重构 FFT 硬件加速器 

分 类 号：TN911.72[电子电信—通信与信息系统]