高安全电子设备中RAM测试算法的设计与实现  

Design and Implementation of a RAM Test Algorithm for High security Electronic Devices

作　　者：杨晓宁 黄保垒 卫一芃 YANG Xiao-ning;HUANG Bao-lei;WEI Yi-peng(Xi′an Aeronautics Computing Technique Research Institute,AVIC,Xi′an 710068,China)

机构地区：[1]航空工业西安航空计算技术研究所,陕西西安710068

出　　处：《航空计算技术》2020年第6期113-115,共3页Aeronautical Computing Technique

基　　金：装备预研联合基金项目资助(6141B05060403)。

摘　　要：为了满足航空高安全电子设备领域的高可靠性和高安全性,解决内存故障给系统带来的不稳定性,针对内存的故障类型和典型的内存测试场景,设计出一种按数据总线、地址总线、存储单元划分功能电路,以总线宽度(字或双字)为测试基准,结合字内组合故障测试码的RAM测试算法。算法通过设置测试步进量调整存储单元测试地址的跨越幅度,满足不同测试场景对测试时间的需求。通过在一些型号项目的上电检测、内存故障定位等应用场景中的验证,算法的时间性能、错误检测率和可配置性等均能满足要求。In order to meet the requirements of high reliability and safety in the field of aviation high safety electronic equipment,and to solve the instability of the system caused by memory failure,this paper designs a functional circuit divided by data bus,address bus and storage unit according to memory fault types and typical memory test scenarios.The bus width(word or double word)is taken as the test benchmark,combined with the word combination fault the ram test algorithm of block test code.The algorithm adjusts the span range of test address by setting test step to meet the test time requirements of different test scenarios.The time performance,error detection rate and configurability of the algorithm can meet the requirements through the verification in some application scenarios such as power on detection and memory fault location.

关 键 词：电子设备 可靠性 RAM测试 MARCH算法 

分 类 号：TP316.2[自动化与计算机技术—计算机软件与理论]